Jicheon Kim

Orcid: 0009-0007-3010-7668

According to our database1, Jicheon Kim authored at least 9 papers between 2013 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Communication-Aware Hybrid Parallelism Mapping for Low-Cost MCM-based DNN Accelerators.
Proceedings of the Design, Automation & Test in Europe Conference, 2026

2025
Live Demonstration: A Scalable CNN Accelerator SoC With a Cost-Effective Chip-to-Chip Adapter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

A Multi-Chip-Module-Based Architecture Simulator for Scaling Vision Transformer Inference.
Proceedings of the IEEE International Conference on Consumer Electronics, 2025

Leveraging Hot Data in a Multi-Tenant Accelerator for Effective Shared Memory Management.
Proceedings of the Design, Automation & Test in Europe Conference, 2025

2024
A Highly-Scalable Deep-Learning Accelerator With a Cost-Effective Chip-to-Chip Adapter and a C2C-Communication-Aware Scheduler.
IEEE J. Emerg. Sel. Topics Circuits Syst., September, 2024

A Scalable Multi-Chip YOLO Accelerator With a Lightweight Inter-Chip Adapter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
Live Demonstration: Layer-wise Configurable CNN Accelerator with High PE Utilization.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2013
Efficient test bitstream generation with an N-way covering algorithm for configurations of high-level syntax elements in video decoders.
IEEE Trans. Consumer Electron., 2013

Generation of efficient bitstreams for functional tests of video decoders.
Proceedings of the IEEE International Conference on Consumer Electronics, 2013


  Loading...