Hyuk-Jae Lee

According to our database1, Hyuk-Jae Lee authored at least 136 papers between 1994 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
A Low-Cost and High-Throughput FPGA Implementation of the Retinex Algorithm for Real-Time Video Enhancement.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Flexibly Connectable Light Field System For Free View Exploration.
IEEE Trans. Multimedia, 2020

Fast Hardware-Based IME With an Idle Cycle and Computational Redundancy Reduction.
IEEE Trans. Circuits Syst. Video Techn., 2020

An Approximate Memory Architecture for Energy Saving in Deep Learning Applications.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

A Stacked Deep MEMC Network for Frame Rate Up Conversion and its Application to HEVC.
IEEE Access, 2020

PCM: Precision-Controlled Memory System for Energy Efficient Deep Neural Network Training.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Zero Block Caching for CNN Applications Running on a Vision DSP.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

Uncertainty-based Object Detector for Autonomous Driving Embedded Platforms.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

2019
A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection.
IEEE Trans. Very Large Scale Integr. Syst., 2019

A High-Throughput Hardware Accelerator for Lossless Compression of a DDR4 Command Trace.
IEEE Trans. Very Large Scale Integr. Syst., 2019

A Novel FPGA Implementation of a Time-to-Digital Converter Supporting Run-Time Estimation and Compensation.
ACM Trans. Reconfigurable Technol. Syst., 2019

Effective Parallelization of a High-Order Graph Matching Algorithm for GPU Execution.
IEEE Trans. Circuits Syst. Video Techn., 2019

Design and Analysis of Area and Power Efficient Approximate Booth Multipliers.
IEEE Trans. Computers, 2019

Integration and Boost of a Read-Modify-Write Module in Phase Change Memory System.
IEEE Trans. Computers, 2019

Segmented Tag Cache: A Novel Cache Organization for Reducing Dynamic Read Energy.
IEEE Trans. Computers, 2019

An Effective DRAM Address Remapping for Mitigating Rowhammer Errors.
IEEE Trans. Computers, 2019

An adaptive hash-based search for integer motion estimation in SCC.
IEICE Electronic Express, 2019

Hardware Design of a Context-Preserving Filter-Reorganized CNN for Super-Resolution.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

HAD-TWL: Hot Address Detection-Based Wear Leveling for Phase-Change Memory Systems with Low Latency.
IEEE Comput. Archit. Lett., 2019

ROI-Based LiDAR Sampling Algorithm in on-Road Environment for Autonomous Driving.
IEEE Access, 2019

Resolution-Preserving Generative Adversarial Networks for Image Enhancement.
IEEE Access, 2019

"Live Demonstration" Ambidextrous Virtual Keyboard Design with Finger Gesture Recognition.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Gaussian YOLOv3: An Accurate and Fast Object Detector Using Localization Uncertainty for Autonomous Driving.
Proceedings of the 2019 IEEE/CVF International Conference on Computer Vision, 2019

A Hardware-Friendly Compression Algorithm for Profiling DDR4 Memory Accesses.
Proceedings of the International Conference on Electronics, Information, and Communication, 2019

Context-Preserving Filter Reorganization for VDSR-Based Super-resolution.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

Fast Detection of Objects Using a YOLOv3 Network for a Vending Machine.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

POSTER: GPU Based Near Data Processing for Image Processing with Pattern Aware Data Allocation and Prefetching.
Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

2018
A Highly Utilized Hardware-Based Merge Mode Estimation with Candidate Level Parallel Execution for High-Efficiency Video Coding.
J. Signal Process. Syst., 2018

SPIHT Algorithm With Adaptive Selection of Compression Ratio Depending on DWT Coefficients.
IEEE Trans. Multimedia, 2018

A Hardware Architecture for the Affine-Invariant Extension of SIFT.
IEEE Trans. Circuits Syst. Video Techn., 2018

Fast Integer Motion Estimation With Bottom-Up Motion Vector Prediction for an HEVC Encoder.
IEEE Trans. Circuits Syst. Video Techn., 2018

A Low-Cost Hardware Design of a 1-D SPIHT Algorithm for Video Display Systems.
IEEE Trans. Consumer Electron., 2018

A Sub-Pixel Gradient Compression Algorithm for Text Image Display on a Smart Device.
IEEE Trans. Consumer Electron., 2018

Optimized Interpolation and Cached Data Access in LUT-Based RGB-to-RGBW Conversion.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Optimal Selection of SRAM Bit-Cell Size for Power Reduction in Video Compression.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Fast hand and finger detection algorithm for interaction on smart display.
Displays, 2018

Compression of smart contents with classification between text and picture blocks using sub-pixel gradient information.
Displays, 2018

Hierarchical Motion Estimation for Small Objects in Frame-Rate Up-Conversion.
IEEE Access, 2018

A New Update Strategy for Blocks with Low Correlation in 3-D Recursive Search.
Proceedings of the IEEE Visual Communications and Image Processing, 2018

Efficient Fixed/Floating-Point Merged Mixed-Precision Multiply-Accumulate Unit for Deep Learning Processors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Power Efficient Approximate Booth Multiplier.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An Approximate Memory Architecture for a Reduction of Refresh Power Consumption in Deep Learning Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A New FPGA Implementation of a Time-to-Digital Converter Supporting Run-Time Estimation of Operating Condition Variation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Ambidextrous Virtual Keyboard Design with Finger Gesture Recognition.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Ray-space360: An extension of ray-space for omnidirectional free viewpoint.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A New Virtual Keyboard with Finger Gesture Recognition for AR/VR Devices.
Proceedings of the Human-Computer Interaction. Interaction Technologies, 2018

2017
Complexity Reduction by Modified Scale-Space Construction in SIFT Generation Optimized for a Mobile GPU.
IEEE Trans. Circuits Syst. Video Techn., 2017

A low-power surveillance video coding system with early background subtraction and adaptive frame memory compression.
IEEE Trans. Consumer Electron., 2017

A hardware-oriented concurrent TZ search algorithm for High-Efficiency Video Coding.
EURASIP J. Adv. Signal Process., 2017

Implementation of the XY2-100 protocol on low-cost microcontroller.
Proceedings of the International SoC Design Conference, 2017

An efficient non-selective adaptive motion compensated frame rate up conversion.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A semi-global motion estimation of a repetition pattern region for frame interpolation.
Proceedings of the 2017 IEEE International Conference on Image Processing, 2017

2016
A Low-Power Video Recording System With Multiple Operation Modes for H.264 and Light-Weight Compression.
IEEE Trans. Multimedia, 2016

A High-Throughput Hardware Design of a One-Dimensional SPIHT Algorithm.
IEEE Trans. Multimedia, 2016

A Novel Hardware Architecture With Reduced Internal Memory for Real-Time Extraction of SIFT in an HD Video.
IEEE Trans. Circuits Syst. Video Techn., 2016

A Novel Hardware Architecture of the Lucas-Kanade Optical Flow for Reduced Frame Memory Access.
IEEE Trans. Circuits Syst. Video Techn., 2016

Merge Mode Estimation for a Hardware-Based HEVC Encoder.
IEEE Trans. Circuits Syst. Video Techn., 2016

RGBW image compression by low-complexity adaptive multi-level block truncation coding.
IEEE Trans. Consumer Electron., 2016

Fixed-Ratio Compression of an RGBW Image and Its Hardware Implementation.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Dense stereo-based real-time ROI generation for on-road obstacle detection.
Proceedings of the International SoC Design Conference, 2016

Fixed-length Golomb-Rice coding by quantization level estimation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

An implementation of an affine BRISK for mobile heterogeneous parallel processors.
Proceedings of the IEEE International Conference on Consumer Electronics, 2016

An adaptive selection of an SRAM cell size for power reduction in an H.264/AVC encoder.
Proceedings of the IEEE International Conference on Consumer Electronics, 2016

A design of a cost-effective look-up table for RGB-to-RGBW conversion.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
An Effective Combination of Power Scaling for H.264/AVC Compression.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Simplified algorithms for rate-distortion optimization in high efficiency video coding.
Displays, 2015

Next generation TV systems and technologies.
Displays, 2015

Highly utilized merge mode estimation for a hardware-based HEVC encoder.
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

2014
An H.264 High-Profile Intra-Prediction with Adaptive Selection Between the Parallel and Pipelined Executions of Prediction Modes.
IEEE Trans. Multimedia, 2014

A cache-aware motion estimation organization for a hardware-based H.264 encoder.
IEEE Trans. Consumer Electron., 2014

Region-constrained Feature Matching with Hierachical Agglomerative Clustering.
Proceedings of the VISAPP 2014, 2014

A VLSI design of real-time and scalable Lucas-Kanade optical flow.
Proceedings of the International Conference on Electronics, Information and Communications, 2014

A low-power hybrid video recording system with H.264/AVC and light-weight compression.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

2013
A Novel Algorithm for Zero Block Detection in High Efficiency Video Coding.
IEEE J. Sel. Top. Signal Process., 2013

Early Decision of Prediction Direction with Hierarchical Correlation for HEVC Compression.
IEICE Trans. Inf. Syst., 2013

Fast merge mode decision for diamond search in High Efficiency Video Coding.
Proceedings of the 2013 Visual Communications and Image Processing, 2013

A low-power video recording system with H.264/AVC and light-weight compression.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

Address generation for lossless frame memory compression in an H.264/AVC encoder.
Proceedings of the IEEE International Conference on Consumer Electronics, 2013

2012
Cascaded Direction Filtering for Fast Multidirectional Inter-Prediction in H.264/AVC Main and High Profile Compression.
IEEE Trans. Circuits Syst. Video Techn., 2012

A Block-Based Pass-Parallel SPIHT Algorithm.
IEEE Trans. Circuits Syst. Video Techn., 2012

A survey of fast mode decision algorithms for inter-prediction and their applications to high efficiency video coding.
IEEE Trans. Consumer Electron., 2012

Reference frame selection in a hardware-based HEVC encoder.
IEICE Electronic Express, 2012

Bitrate control using a heuristic spatial resolution adjustment for a real-time H.264/AVC encoder.
EURASIP J. Adv. Signal Process., 2012

An inter-frame macroblock schedule for memory access reduction in H.264/AVC bi-directional prediction.
Proceedings of the International SoC Design Conference, 2012

A practical hardware design for the keypoint detection in the SIFT algorithm with a reduced memory requirement.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Rotation-invariant hand posture classification with a convexity defect histogram.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
A Fast H.264 Intra Frame Encoder with Serialized Execution of 4 × 4 and 16 × 16 Predictions and Early Termination.
J. Signal Process. Syst., 2011

Memory and computation efficient hardware design for a 3 spatial and temporal layers SVC encoder.
IEEE Trans. Consumer Electron., 2011

Block-based adaptive noise filtering for H.264/AVC compression.
IEEE Trans. Consumer Electron., 2011

An H.264/AVC Decoder with Reduced External Memory Access for Motion Compensation.
IEICE Trans. Inf. Syst., 2011

Power-aware design with various low-power algorithms for an H.264/AVC encoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
A Real-Time H.264/AVC Encoder With Complexity-Aware Time Allocation.
IEEE Trans. Circuits Syst. Video Techn., 2010

Bit plane matching based variable block size motion estimation method and its hardware architecture.
IEEE Trans. Consumer Electron., 2010

Fine-Grain Register Allocation and Instruction Scheduling in a Reference Flow.
Comput. J., 2010

2009
An Adaptive Address Power Saving Method Based on the Prediction of Power Consumption in an AC PDP.
IEEE Trans. Ind. Electron., 2009

Error Propagation Algorithm for Reduction of Errors Due to Total Load and Line Load in a Plasma Panel Display.
IEEE Trans. Circuits Syst. Video Techn., 2009

Two-bit transform based block motion estimation using second derivatives.
IEEE Trans. Consumer Electron., 2009

Reduction of quantization errors caused by dynamic LCD backlight scaling.
IEICE Electronic Express, 2009

A New Frame Memory Compression Algorithm with DPCM and VLC in a 4×4 Block.
EURASIP J. Adv. Signal Process., 2009

A Phase-Based Approach for On-Chip Bus Architecture Optimization.
Comput. J., 2009

Pixel-Parallel SPIHT for frame memory compression.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Fast pipeline schedule for an H.264 intra frame encoder with early termination.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

An SoC Integrating an H.264 Encoder with an ISP.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
A Subfield Coding Algorithm for the Reduction of Gray Level Errors Due to Line Load in a Plasma Display Panel.
IEEE Trans. Circuits Syst. Video Techn., 2008

Reduction of halftoning errors due to line load in a plasma display panel.
IEEE Trans. Consumer Electron., 2008

Wire Optimization for Multimedia SoC and SiP Designs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Motion-Compensated Frame Interpolation for Intra-Mode Blocks.
IEICE Trans. Inf. Syst., 2008

Probabilistic Global Motion Estimation Based on Laplacian Two-Bit Plane Matching for Fast Digital Image Stabilization.
EURASIP J. Adv. Signal Process., 2008

Early Termination and Pipelining for Hardware Implementation of Fast H.264 Intraprediction Targeting Mobile HD Applications.
EURASIP J. Adv. Signal Process., 2008

Speed control for a hardware based H.264/AVC encoder.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

2007
A High-Speed Link Layer Architecture for Low Latency and Memory Cost Reduction.
Comput. J., 2007

Cache Organizations for H.264/AVC Motion Compensation.
Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 2007

A New Frame Recompression Algorithm Integrated with H.264 Video Compression.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A PDP Sub-field Coding Algorithm for the Reduction of Errors due to Line Load Variation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

An Efficient Pipelined Architecture for H.264/AVC Intra Frame Processing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

An Edge-Adaptive Block Matching Algorithm for Error Concealment.
Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, 2007

Block-Level Processing of a Video Object Segmentation Algorithm for Real-Time Systems.
Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, 2007

2006
Integrated Instruction Scheduling and Fine-Grain Register Allocation for Embedded Processors.
Proceedings of the Embedded Computer Systems: Architectures, 2006

Hardware/Software Partitioned Implementation of Real-time Object-oriented Camera for Arbitrary-shaped MPEG-4 Contents.
Proceedings of the 2006 4th Workshop on Embedded Systems for Real-Time Multimedia, 2006

A Parallel and Pipelined Execution of H.264/AVC Intra Prediction.
Proceedings of the Sixth International Conference on Computer and Information Technology (CIT 2006), 2006

2004
A new multi-channel on-chip-bus architecture for system-on-chips.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

2003
Generation of Injective and Reversible Modular Mappings.
IEEE Trans. Parallel Distrib. Syst., 2003

Fine-Grain Register Allocation Based on a Global Spill Costs Analysis.
Proceedings of the Software and Compilers for Embedded Systems, 7th International Workshop, 2003

Register Allocation Based on a Reference Flow Analysis.
Proceedings of the Programming Languages and Systems, First Asian Symposium, 2003

2002
Iterative procedural abstraction for code size reduction.
Proceedings of the International Conference on Compilers, 2002

2001
A Systematic Generation of Initial Register-Reuse Chains for Dependence Minimization.
ACM SIGPLAN Notices, 2001

1998
Automatic Generation of Modular Time-Space Mappings and Data Alignments.
J. VLSI Signal Process., 1998

1997
Modular Mappings and Data Distribution Independent Computations.
Parallel Process. Lett., 1997

Communication-Minimal Partitioning and Data Alignment for Affine Nested Loops.
Comput. J., 1997

Generalized Cannon's Algorithm for Parallel Matrix Multiplication.
Proceedings of the 11th international conference on Supercomputing, 1997

Automatic generation of injective modular mappings.
Proceedings of the 1997 International Conference on Parallel Processing (ICPP '97), 1997

1996
Automatic Generation of Modular Mappings.
Proceedings of the 1996 International Conference on Application-Specific Systems, 1996

1995
Toward data distribution independent parallel matrix multiplication.
Proceedings of IPPS '95, 1995

Conditions of Blocked BLAS-like Algorithms for Data Alignment and Communication Minimization.
Proceedings of the 1995 International Conference on Parallel Processing, 1995

Data Alignments for Modular Time-Space Mappings of BLAS-like Algorithms.
Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995

1994
On the injectivity of modular mappings.
Proceedings of the International Conference on Application Specific Array Processors, 1994


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