Jim Stevens

According to our database1, Jim Stevens authored at least 12 papers between 2006 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2016
The Case for Associative DRAM Caches.
Proceedings of the Second International Symposium on Memory Systems, 2016

Fast full system memory checkpointing with SSD-aware memory controller.
Proceedings of the Second International Symposium on Memory Systems, 2016

2015
Bringing Modern Hierarchical Memory Systems Into Focus: A study of architecture and workload factors on system performance.
Proceedings of the 2015 International Symposium on Memory Systems, 2015

The Semantic Gap Between Software and the Memory System.
Proceedings of the 2015 International Symposium on Memory Systems, 2015

2008
Achieving Programming Model Abstractions for Reconfigurable Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2008

2007
Hybridthreads Compiler: Generation of Application Specific Hardware Thread Cores from C.
Proceedings of the FPL 2007, 2007

Supporting High Level Language Semantics Within Hardware Resident Threads.
Proceedings of the FPL 2007, 2007

Memory Hierarchy for MCSoPC Multithreaded Systems.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

2006
Run-Time Services for Hybrid CPU/FPGA Systems on Chip.
Proceedings of the 27th IEEE Real-Time Systems Symposium (RTSS 2006), 2006

Hthreads: A Computational Model for Reconfigurable Devices.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Enabling a Uniform Programming Model Across the Software/Hardware Boundary.
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

The Case for High Level Programming Models for Reconfigurable Computers.
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006


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