Bruce L. Jacob

, 2017

2016

DRAM Refresh Mechanisms, Penalties, and Trade-Offs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

The 2 PetaFLOP, 3 Petabyte, 9 TB/s, 90 kW Cabinet: A System Architecture for Exascale and Big Data.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2016

The Case for VLIW-CMP as a Building Block for Exascale.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2016

The Case for Associative DRAM Caches.

[BibT_eX]

[DOI]

Proceedings of the Second International Symposium on Memory Systems, 2016

Fast full system memory checkpointing with SSD-aware memory controller.

[BibT_eX]

[DOI]

Jim Stevens

Paul Tschirhart

Proceedings of the Second International Symposium on Memory Systems, 2016

Low Latency, High Bisection-Bandwidth Networks for Exascale Memory Systems.

[BibT_eX]

[DOI]

Proceedings of the Second International Symposium on Memory Systems, 2016

2015

Bringing Modern Hierarchical Memory Systems Into Focus: A study of architecture and workload factors on system performance.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Symposium on Memory Systems, 2015

The Semantic Gap Between Software and the Memory System.

[BibT_eX]

[DOI]

Jim Stevens

Paul Tschirhart

Proceedings of the 2015 International Symposium on Memory Systems, 2015

Flexible auto-refresh: enabling scalable and energy-efficient DRAM refresh reductions.

[BibT_eX]

[DOI]

Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

2014

High-bandwidth, high-capacity, low-power memory systems.

[BibT_eX]

[DOI]

Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

2013

Coordinated refresh: Energy efficient techniques for DRAM refresh scheduling.

[BibT_eX]

[DOI]

Ishwar Bhati

Zeshan Chishti

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Technology comparison for large last-level caches (L<sup>3</sup>Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

2012

Energy-Efficient Cached DIMM Architecture.

[BibT_eX]

[DOI]

Mu-Tien Chang

Joe Gross

Proceedings of the 20th IEEE International Symposium on Modeling, 2012

Buffer-on-board memory systems.

[BibT_eX]

[DOI]

Elliott Cooper-Balis

Paul Rosenfeld

Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

2011

The structural simulation toolkit.

[BibT_eX]

[DOI]

SIGMETRICS Perform. Evaluation Rev., 2011

DRAMSim2: A Cycle Accurate Memory System Simulator.

[BibT_eX]

[DOI]

Paul Rosenfeld

Elliott Cooper-Balis

IEEE Comput. Archit. Lett., 2011

An analytical model to estimate PCM failure probability due to process variations.

[BibT_eX]

[DOI]

Mu-Tien Chang

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Let there be light!: the future of memory systems is photonics and 3D stacking.

[BibT_eX]

[DOI]

Proceedings of the 2011 ACM SIGPLAN workshop on Memory Systems Performance and Correctness: held in conjunction with PLDI '11, 2011

2010

Fine-Grained Activation for Power Reduction in DRAM.

[BibT_eX]

[DOI]

Elliott Cooper-Balis

IEEE Micro, 2010

2009

The Memory System: You Can't Avoid It, You Can't Ignore It, You Can't Fake It

[BibT_eX]

[DOI]

Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01724-7, 2009

The performance of PC solid-state disks (SSDs) as a function of bandwidth, concurrency, device architecture, and system organization.

[BibT_eX]

[DOI]

Cagdas Dirik

Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

2008

Memory Systems: Cache, DRAM, Disk

[BibT_eX]

[DOI]

Spencer W. Ng

David T. Wang

Morgan Kaufmann, ISBN: 978-0-12-379751-3, 2008

2007

Accurate and fast system-level power modeling: An XScale-based case study.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2007

Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling.

[BibT_eX]

[DOI]

Proceedings of the 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 2007

2006

In-Line Interrupt Handling and Lock-Up Free Translation Lookaside Buffers (TLBs).

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2006

Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm).

[BibT_eX]

[DOI]

Samuel Rodríguez

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Last level cache (LLC) performance of data mining workloads on a CMP - a case study of parallel bioinformatics workloads.

[BibT_eX]

[DOI]

Matthew Mattina

Proceedings of the 12th International Symposium on High-Performance Computer Architecture, 2006

Modeling heterogeneous SoCs with SystemC: a digital/MEMS case study.

[BibT_eX]

[DOI]

Ankush Varma

Muhammad Yaqub Afridi

Proceedings of the 2006 International Conference on Compilers, 2006

2005

DRAMsim: a memory system simulator.

[BibT_eX]

[DOI]

David Wang

Brinda Ganesh

Nuengwong Tuaycharoen

Kathleen Baynes

SIGARCH Comput. Archit. News, 2005

BioBench: A Benchmark Suite of Bioinformatics Applications.

[BibT_eX]

[DOI]

Kursad Albayraktaroglu

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005

Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

TERPS: the embedded reliable processing system.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Performance characteristics of MAUI: an intelligent memory system architecture.

[BibT_eX]

[DOI]

Justin Teller

Charles B. Silio Jr.

Proceedings of the 2005 workshop on Memory System Performance, 2005

2004

Extended Split-Issue: Enabling Flexibility in the Hardware Implementation of NUAL VLIW DSPs.

[BibT_eX]

[DOI]

Bharath Iyer

Sadagopan Srinivasan

Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004

2003

Introduction to the two special issues on memory.

[BibT_eX]

[DOI]

Shuvra S. Bhattacharyya

ACM Trans. Embed. Comput. Syst., 2003

The Performance and Energy Consumption of Embedded Real-Time Operating Systems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2003

A Case for Studying DRAM Issues at the System Level.

[BibT_eX]

[DOI]

IEEE Micro, 2003

Hardware support for real-time operating systems.

[BibT_eX]

[DOI]

Paul Kohout

Brinda Ganesh

Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

A control-theoretic approach to dynamic voltage scheduling.

[BibT_eX]

[DOI]

Ankush Varma

Brinda Ganesh

Mainak Sen

Suchismita Roy Choudhury

Lakshmi Srinivasan

Proceedings of the International Conference on Compilers, 2003

2001

Uniprocessor Virtual Memory without TLBs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2001

High-Performance DRAMs in Workstation Environments.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2001

Concurrency, latency, or system overhead: which has the largest impact on uniprocessor DRAM-system performance?.

[BibT_eX]

[DOI]

Vinodh Cuppu

Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001

In-Line Interrupt Handling for Software-Managed TLBs.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Improving the Precise Interrupt Mechanism of Software-Managed TLB Miss Handlers.

[BibT_eX]

[DOI]

Proceedings of the High Performance Computing - HiPC 2001, 8th International Conference, 2001

Transparent data-memory organizations for digital signal processors.

[BibT_eX]

[DOI]

Sadagopan Srinivasan

Vinodh Cuppu

Proceedings of the 2001 International Conference on Compilers, 2001

The performance and energy consumption of three embedded real-time operating systems.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Conference on Compilers, 2001

2000

The New DRAM Interfaces: SDRAM, RDRAM and Variants.

[BibT_eX]

[DOI]

Brian Davis

Proceedings of the High Performance Computing, Third International Symposium, 2000

1999

A Performance Comparison of Contemporary DRAM Architectures.

[BibT_eX]

[DOI]

Proceedings of the 26th Annual International Symposium on Computer Architecture, 1999

Fifth Annual Workshop on Computer Education.

[BibT_eX]

[DOI]

David R. Kaeli

Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, 1999

1998

Virtual memory in contemporary microprocessors.

[BibT_eX]

[DOI]

IEEE Micro, 1998

Virtual Memory: Issues of Implementation.

[BibT_eX]

[DOI]

Computer, 1998

A Look at Several Memory Management Units, TLB-Refill Mechanisms, and Page Table Organizations.

[BibT_eX]

[DOI]

Proceedings of the ASPLOS-VIII Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, 1998

1997

Software-oriented memory-management design.

[BibT_eX]

[DOI]

PhD thesis, 1997

A Comment on "An Analytical Model for Designing Memory Hierarchies".

[BibT_eX]

[DOI]