Shih-Lien Lu
According to our database1,
Shih-Lien Lu
authored at least 88 papers
between 1988 and 2021.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2016, "For contributions to low-voltage microarchitecture and approximate computing".
Timeline
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On csauthors.net:
Bibliography
2021
O2MD²: A New Post-Quantum Cryptosystem With One-to-Many Distributed Key Management Based on Prime Modulo Double Encapsulation.
IEEE Access, 2021
2020
CompAcc: Efficient Hardware Realization for Processing Compressed Neural Networks Using Accumulator Arrays.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020
2019
IEEE Des. Test, 2019
A Reliable, Low-Cost, Low-Energy Physically Unclonable Function Circuit Through Effective Filtering.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019
2018
Proceedings of the 2018 International Symposium on VLSI Design, 2018
A FeFET Based Processing-In-Memory Architecture for Solving Distributed Least-Square Optimizations.
Proceedings of the 76th Device Research Conference, 2018
2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
Proceedings of the 17th International Conference on Parallel and Distributed Computing, 2016
Proceedings of the 35th IEEE International Performance Computing and Communications Conference, 2016
2015
A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs.
Proceedings of the Symposium on VLSI Circuits, 2015
Proceedings of the VLSI Design, Automation and Test, 2015
Proceedings of the 48th International Symposium on Microarchitecture, 2015
Bringing Modern Hierarchical Memory Systems Into Focus: A study of architecture and workload factors on system performance.
Proceedings of the 2015 International Symposium on Memory Systems, 2015
Flexible auto-refresh: enabling scalable and energy-efficient DRAM refresh reductions.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015
2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Recycled Error Bits: Energy-Efficient Architectural Support for Floating Point Accuracy.
Proceedings of the International Conference for High Performance Computing, 2014
Author retrospective for bloom filtering cache misses for accurate data speculation and prefetching.
Proceedings of the ACM International Conference on Supercomputing 25th Anniversary Volume, 2014
Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014
2013
Reducing cache and TLB power by exploiting memory region and privilege level semantics.
J. Syst. Archit., 2013
Recycled Error Bits: Energy-Efficient Architectural Support for Higher Precision Floating Point.
CoRR, 2013
Guided Region-Based GPU Scheduling: Utilizing Multi-thread Parallelism to Hide Memory Latency.
Proceedings of the 27th IEEE International Symposium on Parallel and Distributed Processing, 2013
Proceedings of the 2013 21st IEEE International Conference on Network Protocols, 2013
Technology comparison for large last-level caches (L<sup>3</sup>Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
IEEE Trans. Computers, 2011
IEEE J. Solid State Circuits, 2011
IEEE J. Solid State Circuits, 2011
Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011
Proceedings of the Design, Automation and Test in Europe, 2011
2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010
Automatic multithreaded pipeline synthesis from transactional datapath specifications.
Proceedings of the 47th Design Automation Conference, 2010
Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology.
IEEE J. Solid State Circuits, 2009
Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance.
IEEE J. Solid State Circuits, 2009
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Proceedings of the 46th Design Automation Conference, 2009
Proceedings of the CSIE 2009, 2009 WRI World Congress on Computer Science and Information Engineering, March 31, 2009
2008
Proceedings of the Wiley Encyclopedia of Computer Science and Engineering, 2008
ACM Trans. Reconfigurable Technol. Syst., 2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008
Proceedings of the FPL 2008, 2008
2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the 25th International Conference on Computer Design, 2007
An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems.
Proceedings of the FPL 2007, 2007
Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, 2007
2006
Proceedings of the 2006 IEEE Hot Chips 18 Symposium (HCS), 2006
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006
2005
Proceedings of the 19th Annual International Conference on Supercomputing, 2005
A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications.
Proceedings of the 31st European Solid-State Circuits Conference, 2005
Proceedings of the Second Conference on Computing Frontiers, 2005
2004
Proceedings of the Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, 2004
2003
A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme.
IEEE J. Solid State Circuits, 2003
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003
2002
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002
Proceedings of the 16th international conference on Supercomputing, 2002
Proceedings of the 2002 International Conference on Dependable Systems and Networks (DSN 2002), 2002
2001
2000
Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000
1998
Proceedings of the Fourth International Symposium on High-Performance Computer Architecture, Las Vegas, Nevada, USA, January 31, 1998
1997
Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), 1997
1996
IEEE Trans. Very Large Scale Integr. Syst., 1996
1995
IEEE Trans. Very Large Scale Integr. Syst., 1995
IEEE Trans. Very Large Scale Integr. Syst., 1995
1988
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988