Jin-Ho Ahn

According to our database1, Jin-Ho Ahn authored at least 20 papers between 2004 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


On csauthors.net:


Chain-Based Approach for Fast Through-Silicon-Via Coupling Delay Estimation.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Developing a cognitive evaluation method for serious game engineers.
Clust. Comput., 2014

Implementation of an LED tile controller for high-quality image display.
Displays, 2013

NoRSE: noise reduction and state evaluator for high-frequency single event traces.
Bioinform., 2012

Development of a walking game for the elderly using controllers of hand buttons and foot boards.
Proceedings of the 17th International Conference on Computer Games, 2012

Noise-Tolerant DAC BIST Scheme Using Integral Calculus Approach.
IEICE Trans. Electron., 2011

A Memory-Efficient Pattern Matching with Hardware-Based Bit-Split String Matchers for Deep Packet Inspection.
IEICE Trans. Commun., 2010

A Hardware-Efficient Pattern Matching Architecture Using Process Element Tree for Deep Packet Inspection.
IEICE Trans. Commun., 2010

A high performance network-on-chip scheme using lossless data compression.
IEICE Electron. Express, 2010

A memory-efficient heterogeneous parallel pattern matching scheme in deep packet inspection.
IEICE Electron. Express, 2010

An Efficient Hardware Architecture of the A-star Algorithm for the Shortest Path Search Engine.
Proceedings of the International Conference on Networked Computing and Advanced Information Management, 2009

An Ant Colony Optimization Approach for the Preference-Based Shortest Path Search.
Proceedings of the Communication and Networking, 2009

Total Energy Minimization of Real-Time Tasks in an On-Chip Multiprocessor Using Dynamic Voltage Scaling Efficiency Metric.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

MTR-Fill: A Simulated Annealing-Based X-Filling Technique to Reduce Test Power Dissipation for Scan-Based Designs.
IEICE Trans. Inf. Syst., 2008

System-Level Development and Verification of the FlexRay Communication Controller Model Based on SystemC.
Proceedings of the Second International Conference on Future Generation Communication and Networking, 2008

System on a Chip Implementation of Social Insect Behavior for Adaptive Network Routing.
Proceedings of the Computational Intelligence, 2006

SoC Test Scheduling Algorithm Using ACO-Based Rectangle Packing.
Proceedings of the Computational Intelligence, 2006

A Practical Test Scheduling Using Network-Based TAM in Network on Chip Architecture.
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005

Route Reinforcement for Efficient QoS Routing Based on Ant Algorithm.
Proceedings of the Information Networking, 2004

RAIN (RAndom Insertion) Scheduling Algorithm for SoC Test.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004