Woo-Chan Park
Orcid: 0000-0002-9249-2887
According to our database1,
Woo-Chan Park
authored at least 56 papers
between 1999 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
Sensors, August, 2023
Sensors, January, 2023
An Architecture and Implementation of Real-Time Sound Propagation Hardware for Mobile Devices.
Proceedings of the SIGGRAPH Asia 2023 Conference Papers, 2023
2022
Effective Algorithm to Control Depth Level for Performance Improvement of Sound Tracing.
J. Web Eng., 2022
2021
Lossless Compression Algorithm and Architecture for Reduced Memory Bandwidth Requirement with Improved Prediction Based on the Multiple DPCM Golomb-Rice Algorithm.
J. Web Eng., 2021
An Implementation of Multi-Chip Architecture for Real-Time Ray Tracing Based on Parallel Frame Rendering.
IEEE Access, 2021
An Effective Burst Access Scheme for Lossless Frame Buffer Compression on a Video Decoder.
IEEE Access, 2021
2020
IEEE Access, 2020
IEEE Access, 2020
2019
A Practically Applicable Performance Prediction Model Based on Capabilities of Texture Mapping Units for Mobile GPUs.
IEEE Access, 2019
An Effective Algorithm and Architecture for the High-Throughput Lossless Compression of High-Resolution Images.
IEEE Access, 2019
2018
Real-time 3D Audio Downmixing System based on Sound Rendering for the Immersive Sound of Mobile Virtual Reality Applications.
KSII Trans. Internet Inf. Syst., 2018
2017
An Effective Viewport Resolution Scaling Technique to Reduce the Power Consumption in Mobile GPUs.
KSII Trans. Internet Inf. Syst., 2017
Real-time sound propagation hardware accelerator for immersive virtual reality 3D audio.
Proceedings of the 21st ACM SIGGRAPH Symposium on Interactive 3D Graphics and Games, 2017
2016
Multim. Tools Appl., 2016
2015
IEEE Trans. Vis. Comput. Graph., 2015
2014
ACM Trans. Graph., 2014
Effective traversal algorithms and hardware architecture for pyramidal inverse displacement mapping.
Comput. Graph., 2014
Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014
2013
A pixel pipeline architecture with selective z-test scheme for 3D graphics processors.
Microprocess. Microsystems, 2013
J. Syst. Archit., 2013
IEICE Trans. Inf. Syst., 2013
IEICE Electron. Express, 2013
2012
Erratum: Efficient ray sorting for the tracing of incoherent rays [IEICE Electronics Express Vol.9 (2012), No 9 pp 849-854].
IEICE Electron. Express, 2012
IEICE Electron. Express, 2012
2011
ACM Trans. Graph., 2011
A Lossless Color Image Compression Architecture Using a Parallel Golomb-Rice Hardware CODEC.
IEEE Trans. Circuits Syst. Video Technol., 2011
An effective depth data memory system using an escape count buffer for 3D rendering processors.
IEICE Electron. Express, 2011
The design of a texture mapping unit with effective MIP-map level selection for real-time ray tracing.
IEICE Electron. Express, 2011
IEICE Electron. Express, 2011
2010
IEICE Electron. Express, 2010
IEICE Electron. Express, 2010
2008
An Effective Load Balancing Scheme for 3D Texture-Based Sort-Last Parallel Volume Rendering on GPU Clusters.
IEICE Trans. Inf. Syst., 2008
2007
J. Syst. Archit., 2007
J. Inf. Sci. Eng., 2007
IET Comput. Digit. Tech., 2007
2006
IEEE Trans. Computers, 2006
A Processor Architecture with Effective Memory System for Sort-Last Parallel Rendering.
Proceedings of the Architecture of Computing Systems, 2006
2005
Microprocess. Microsystems, 2005
2004
IEEE Trans. Computers, 2004
IEICE Trans. Inf. Syst., 2004
A Bandwidth Reduction Scheme for 3D Texture-Based Volume Rendering on Commodity Graphics Hardware.
Proceedings of the Computational Science and Its Applications, 2004
A Floating Point Divider Performing IEEE Rounding and Quotient Conversion in Parallel.
Proceedings of the Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, 2004
Proceedings of the Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, 2004
Proceedings of the Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, 2004
2003
IEEE Trans. Computers, 2003
An effective out-of-order execution control scheme for an embedded floating point coprocessor.
Microprocess. Microsystems, 2003
2002
Design of a Single Pass Rendering Pipeline for Occlusion Culling.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2002
A Pipelined Tiling-Traversal Unit for High Performance 3D Rendering Processor.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2002
Proceedings of the EurAsia-ICT 2002: Information and Communication Technology, 2002
A Mid-Texturing Pixel Rasterization Pipeline Architecture for 3D Rendering Processors.
Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002
2001
Proceedings of the 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 2001
1999
J. Syst. Archit., 1999