Jinghao Ye

Orcid: 0000-0001-6643-9321

According to our database1, Jinghao Ye authored at least 8 papers between 2017 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2021
Power-Efficient Deep Convolutional Neural Network Design Through Zero-Gating PEs and Partial-Sum Reuse Centric Dataflow.
IEEE Access, 2021

2020
Faithfully Truncated Adder-Based Area-Power Efficient FIR Design with Predefined Output Accuracy.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020

A High-Performance Symmetric Hybrid Form Design for High-Order FIR Filters.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020

2019
Static Error Analysis and Optimization of Faithfully Truncated Adders for Area-Power Efficient FIR Designs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

An Adder-Segmentation-based FIR for High Speed Signal Processing.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

A Zero-Gating Processing Element Design for Low-Power Deep Convolutional Neural Networks.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

A Bit-Segmented Adder Chain based Symmetric Transpose Two-Block FIR Design for High-Speed Signal Processing.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

2017
A low cost and high speed CSD-based symmetric transpose block FIR implementation.
Proceedings of the 12th IEEE International Conference on ASIC, 2017


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