Jingxiang Hou

According to our database, Jingxiang Hou authored at least 4 papers between 2025 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

TEMP: A Memory Efficient Physical-Aware Tensor Partition-Mapping Framework on Wafer-Scale Chips.

Huizheng Wang, Taiquan Wei, Zichuan Wang, Dingcheng Jiang, Qize Yang, Jiaxin Liu, Jingxiang Hou, Chao Li, Jinyi Deng, Yang Hu, Shouyi Yin

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2026

WATOS: Efficient LLM Training Strategies and Architecture Co-Exploration for Wafer-Scale Chip.

Huizheng Wang, Zichuan Wang, Hongbin Wang, Jingxiang Hou, Taiquan Wei, Chao Li, Yang Hu, Shouyi Yin

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2026

MoEntwine: Unleashing the Potential of Wafer-Scale Chips for Large-Scale Expert Parallel Inference.

Xinru Tang, Jingxiang Hou, Dingcheng Jiang, Taiquan Wei, Jiaxin Liu, Jinyi Deng, Huizheng Wang, Qize Yang, Haoran Shang, Chao Li, Yang Hu, Shouyi Yin

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2026

2025

WSC-LLM: Efficient LLM Service and Architecture Co-exploration for Wafer-scale Chips.

Zheng Xu, Dehao Kong, Jiaxin Liu, Jinxi Li, Jingxiang Hou, Xu Dai, Chao Li, Shaojun Wei, Yang Hu, Shouyi Yin

Proceedings of the 52nd Annual International Symposium on Computer Architecture, 2025