Taiquan Wei

According to our database, Taiquan Wei authored at least 9 papers between 2025 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

Designing Spatial Architectures for Sparse Attention: STAR Accelerator via Cross-Stage Tiling.

Huizheng Wang, Taiquan Wei, Hongbin Wang, Zichuan Wang, Xinru Tang, Zhiheng Yue, Shaojun Wei, Yang Hu, Shouyi Yin

IEEE Trans. Computers, March, 2026

TEMP: A Memory Efficient Physical-Aware Tensor Partition-Mapping Framework on Wafer-Scale Chips.

Huizheng Wang, Taiquan Wei, Zichuan Wang, Dingcheng Jiang, Qize Yang, Jiaxin Liu, Jingxiang Hou, Chao Li, Jinyi Deng, Yang Hu, Shouyi Yin

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2026

WATOS: Efficient LLM Training Strategies and Architecture Co-Exploration for Wafer-Scale Chip.

Huizheng Wang, Zichuan Wang, Hongbin Wang, Jingxiang Hou, Taiquan Wei, Chao Li, Yang Hu, Shouyi Yin

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2026

MoEntwine: Unleashing the Potential of Wafer-Scale Chips for Large-Scale Expert Parallel Inference.

Xinru Tang, Jingxiang Hou, Dingcheng Jiang, Taiquan Wei, Jiaxin Liu, Jinyi Deng, Huizheng Wang, Qize Yang, Haoran Shang, Chao Li, Yang Hu, Shouyi Yin

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2026

2025

BETA: A Bit-Grained Transformer Attention Accelerator With Efficient Early Termination.

Huizheng Wang, Hongbin Wang, Zhiheng Yue, Jingyao Liu, Taiquan Wei, Shaojun Wei, Yang Hu, Shouyi Yin

IEEE Trans. Circuits Syst. II Express Briefs, October, 2025

MCBP: A Memory-Compute Efficient LLM Inference Accelerator Leveraging Bit-Slice-enabled Sparsity and Repetitiveness.

Huizheng Wang, Zichuan Wang, Zhiheng Yue, Yousheng Long, Taiquan Wei, Jianxun Yang, Yang Wang, Chao Li, Shaojun Wei, Yang Hu, Shouyi Yin

Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture, 2025

PD Constraint-aware Physical/Logical Topology Co-Design for Network on Wafer.

Qize Yang, Taiquan Wei, Sihan Guan, Chengran Li, Haoran Shang, Jinyi Deng, Huizheng Wang, Chao Li, Lei Wang, Yan Zhang, Shouyi Yin, Yang Hu

Proceedings of the 52nd Annual International Symposium on Computer Architecture, 2025

Segmentation-Aware Optimization of Collective for Waferscale Chips.

Qize Yang, Jiaxin Liu, Taiquan Wei, Yuxin Jin, Shouyi Yin, Yang Hu

Proceedings of the Advanced Parallel Processing Technologies, 2025

Spatial-Aware Orchestration of LLM Attention on Waferscale Chips.

Taiquan Wei, Huizheng Wang, Zichuan Wang, Shouyi Yin, Yang Hu

Proceedings of the Advanced Parallel Processing Technologies, 2025