Huizheng Wang

Orcid: 0000-0002-9763-8208

According to our database1, Huizheng Wang authored at least 31 papers between 2018 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
Designing Spatial Architectures for Sparse Attention: STAR Accelerator via Cross-Stage Tiling.
IEEE Trans. Computers, March, 2026

PADE: A Predictor-Free Sparse Attention Accelerator via Unified Execution and Stage Fusion.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2026

TEMP: A Memory Efficient Physical-Aware Tensor Partition-Mapping Framework on Wafer-Scale Chips.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2026

WATOS: Efficient LLM Training Strategies and Architecture Co-Exploration for Wafer-Scale Chip.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2026

MoEntwine: Unleashing the Potential of Wafer-Scale Chips for Large-Scale Expert Parallel Inference.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2026

ReThermal: Co-Design of Thermal-Aware Static and Dynamic Scheduling for LLM Training on Liquid-Cooled Wafer-Scale Chips.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2026

BitStopper: An Efficient Transformer Attention Accelerator via Stage-fusion and Early Termination.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

LAPA: Log-Domain Prediction-Driven Dynamic Sparsity Accelerator for Transformer Model.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025
BETA: A Bit-Grained Transformer Attention Accelerator With Efficient Early Termination.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2025

CV-CIM: A Hybrid Domain Xor-Derived Similarity-Aware Computation-in-Memory Supporting Cost-Volume Construction.
IEEE J. Solid State Circuits, February, 2025

MCBP: A Memory-Compute Efficient LLM Inference Accelerator Leveraging Bit-Slice-enabled Sparsity and Repetitiveness.
Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture, 2025

PD Constraint-aware Physical/Logical Topology Co-Design for Network on Wafer.
Proceedings of the 52nd Annual International Symposium on Computer Architecture, 2025

Spatial-Aware Orchestration of LLM Attention on Waferscale Chips.
Proceedings of the Advanced Parallel Processing Technologies, 2025

2024
Robust Wideband Interference Suppression Method for GNSS Array Antenna Receiver via Hybrid Beamforming Technique.
Remote. Sens., June, 2024

SOFA: A Compute-Memory Optimized Sparsity Accelerator via Cross-Stage Coordinated Tiling.
CoRR, 2024

PALM: A Efficient Performance Simulator for Tiled Accelerators with Large-scale Model Training.
CoRR, 2024

SOFA: A Compute-Memory Optimized Sparsity Accelerator via Cross-Stage Coordinated Tiling.
Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024

Code Length Compatible Belief Propagation Polar Decoder Based on Folding and Unfolding.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Exploiting Similarity Opportunities of Emerging Vision AI Models on Hybrid Bonding Architecture.
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

2023
An Efficient Approximate Expectation Propagation Detector With Block-Diagonal Neumann-Series.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2023

A DSP-Purposed REconfigurable Acceleration Machine (DREAM) for High Energy Efficiency MIMO Signal Processing.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023

Wafer-scale Computing: Advancements, Challenges, and Future Perspectives.
CoRR, 2023

CV-CIM: A 28nm XOR-Derived Similarity-Aware Computation-in-Memory for Cost-Volume Construction.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022
Efficient MMSE-PIC Detection for Polar-Coded System Using Tree-Structured Gray Codes.
IEEE Wirel. Commun. Lett., 2022

An Efficient Stochastic Convolution Architecture Based on Fast FIR Algorithm.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Approximate Computation for Baseband Processing.
Proceedings of the Approximate Computing, 2022

2021
An Efficient Detector for Massive MIMO Based on Improved Matrix Partition.
IEEE Trans. Signal Process., 2021

2020
Efficient stochastic successive cancellation list decoder for polar codes.
Sci. China Inf. Sci., 2020

2019
A New Uplink Channel Estimation Architecture for Massive MIMO Systems with PDMA.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
NEUTag's Classification System for Zhihu Questions Tagging Task.
Proceedings of the Natural Language Processing and Chinese Computing, 2018

Low-Complexity Winograd Convolution Architecture Based on Stochastic Computing.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018


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