Dingcheng Jiang
Orcid: 0009-0004-4379-694X
According to our database1,
Dingcheng Jiang authored at least 8 papers
between 2024 and 2026.
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Bibliography
2026
FACE: Fully Overlapped PD Scheduling and Multi-Level Architecture Co-Exploration on Wafer.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2026
TEMP: A Memory Efficient Physical-Aware Tensor Partition-Mapping Framework on Wafer-Scale Chips.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2026
MoEntwine: Unleashing the Potential of Wafer-Scale Chips for Large-Scale Expert Parallel Inference.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2026
Proceedings of the 31st ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2026
2025
An Energy-Efficient, High-Frame-Rate, and Reconfigurable EKF-SLAM Processor With Full Acceleration for Autonomous Mobile Robots.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2025
Cramming a Data Center into One Cabinet, a Co-Exploration of Computing and Hardware Architecture of Waferscale Chip.
Proceedings of the 52nd Annual International Symposium on Computer Architecture, 2025
2024
Tackling the Dynamicity in a Production LLM Serving System with SOTA Optimizations via Hybrid Prefill/Decode/Verify Scheduling on Efficient Meta-kernels.
CoRR, 2024
Live Demonstration: A Reconfigurable, Energy-efficient and High-frame-rate EKF-SLAM Accelerator Based SoC Design for Autonomous Mobile Robot Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024