Joe Baylon

According to our database, Joe Baylon authored at least 6 papers between 2014 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

Analysis of Systematic Losses in Hybrid Envelope Tracking Modulators.

Luke Renaud, Joe Baylon, Srinivasan Gopal, Md. Aminul Hoque, Deukhyoun Heo

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018

A 16-Gb/s Low-Power Inductorless Wideband Gain-Boosted Baseband Amplifier With Skewed Differential Topology for Wireless Network-on-Chip.

Joe Baylon, Xinmin Yu, Srinivasan Gopal, Reza Molavi, Shahriar Mirabbasi, Partha Pratim Pande, Deukhyoun Heo

IEEE Trans. Very Large Scale Integr. Syst., 2018

A Spatial Multi-Bit Sub-1-V Time-Domain Matrix Multiplier Interface for Approximate Computing in 65-nm CMOS.

Srinivasan Gopal, Pawan Agarwal, Joe Baylon, Luke Renaud, Sheikh Nijam Ali, Partha Pratim Pande, Deukhyoun Heo

IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

A 28GHz 41%-PAE linear CMOS power amplifier using a transformer-based AM-PM distortion-correction technique for 5G phased arrays.

Sheikh Nijam Ali, Pawan Agarwal, Joe Baylon, Srinivasan Gopal, Luke Renaud, Deukhyoun Heo

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017

A Reconfigurable Wireless NoC for Large Scale Microbiome Community Analysis.

Xian Li, Karthi Duraisamy, Joe Baylon, Turbo Majumder, Guopeng Wei, Paul Bogdan, Deukhyoun Heo, Partha Pratim Pande

IEEE Trans. Computers, 2017

2014

Architecture and Design of Multichannel Millimeter-Wave Wireless NoC.

Xinmin Yu, Joe Baylon, Paul Wettin, Deuk Hyoun Heo, Partha Pratim Pande, Shahriar Mirabbasi

IEEE Des. Test, 2014