Turbo Majumder

According to our database1, Turbo Majumder authored at least 20 papers between 2010 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2020
A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2X-Bandwidth Burst 6T-SRAM for Memory Bandwidth Limited Workloads.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2017
A Reconfigurable Wireless NoC for Large Scale Microbiome Community Analysis.
IEEE Trans. Computers, 2017

A Sub-cm<sup>3</sup> Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications.
IEEE J. Solid State Circuits, 2017

2016
Network-on-Chip-Enabled Multicore Platforms for Parallel Model Predictive Control.
IEEE Trans. Very Large Scale Integr. Syst., 2016

An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015
NoC Architectures as Enablers of Biological Discovery for Personalized and Precision Medicine.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

NoC router using STT-MRAM based hybrid buffers with error correction and limited flit retransmission.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Efficient Estimation of Non-stationary Traffic Parameters on Networks-on-Chip.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

On-chip network-enabled many-core architectures for computational biology applications.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

NoC-enabled multicore architectures for stochastic analysis of biomolecular reactions.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Wireless NoC Platforms With Dynamic Task Allocation for Maximum Likelihood Phylogeny Reconstruction.
IEEE Des. Test, 2014

Hardware Accelerators in Computational Biology: Application, Potential, and Challenges.
IEEE Des. Test, 2014

2013
High-throughput, energy-efficient network-on-chip-based hardware accelerators.
Sustain. Comput. Informatics Syst., 2013

Network-on-Chip with Long-Range Wireless Links for High-Throughput Scientific Computation.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

2012
On-Chip Network-Enabled Multicore Platforms Targeting Maximum Likelihood Phylogeny Reconstruction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

NoC-Based Hardware Accelerator for Breakpoint Phylogeny.
IEEE Trans. Computers, 2012

2011
Accelerating Maximum Likelihood Based Phylogenetic Kernels Using Network-on-Chip.
Proceedings of the 23rd International Symposium on Computer Architecture and High Performance Computing, 2011

2010
Hardware accelerators for biocomputing: A survey.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

An optimized NoC architecture for accelerating TSP kernels in breakpoint median problem.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010


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