John J. Paulos

According to our database1, John J. Paulos authored at least 15 papers between 1984 and 1997.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

1997
Toward a general-purpose analog VLSI neural network with on-chip learning.
IEEE Trans. Neural Networks, 1997

An analog VLSI neural network with on-chip perturbation learning.
IEEE J. Solid State Circuits, 1997

1995
Template-based MOSFET device model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

1994
A neural network learning algorithm tailored for VLSI implementation.
IEEE Trans. Neural Networks, 1994

Building Blocks for a Temperature-Compensated Analog VLSI Neural Network with On-Chip Learning.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
Interpolation of MOSFET table data in width, length, and temperature.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

1991
A Microprocessor-Based Implantable Telemetry System.
Computer, 1991

1990
Scalable VLSI implementations for neural networks.
J. VLSI Signal Process., 1990

Table-based modeling of delta-sigma modulators using ZSIM.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

The Effects of Precision Constraints in a Backpropagation Learning Network.
Neural Comput., 1990

A custom microprocessor for implantable telemetry systems.
Proceedings of the Third Annual IEEE Symposium on Computer-Based Medical Systems (CBMS'90), 1990

1989
Switch-level simulation of total dose effects on CMOS VLSI circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

1988
A VLSI architecture for feedforward networks with integral back-propagation.
Neural Networks, 1988

1987
An analysis of sinusoidally excited delta-sigma modulators.
Proceedings of the IEEE International Conference on Acoustics, 1987

1984
Measurement and modeling of small-geometry MOS transistor capacitances.
PhD thesis, 1984


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