Paul D. Franzon

Orcid: 0000-0002-6048-5770

Affiliations:
  • North Carolina State University, Raleigh, USA


According to our database1, Paul D. Franzon authored at least 139 papers between 1987 and 2023.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2006, "For contributions to chip-package codesign.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
A Deep Transfer Learning Design Rule Checker With Synthetic Training.
IEEE Des. Test, February, 2023

DepthGraphNet: Circuit Graph Isomorphism Detection via Siamese-Graph Neural Networks.
Proceedings of the 5th ACM/IEEE Workshop on Machine Learning for CAD, 2023

Thermal Cycling and Fatigue Life Analysis of a Laterally Conducting GaN-based Power Package.
Proceedings of the IEEE International 3D Systems Integration Conference, 2023

Chiplet Set For Artificial Intelligence.
Proceedings of the IEEE International 3D Systems Integration Conference, 2023

Thermal Estimation for 3D-ICs Through Generative Networks.
Proceedings of the IEEE International 3D Systems Integration Conference, 2023

2022
Design Obfuscation Through 3-D Split Fabrication With Smart Partitioning.
IEEE Trans. Very Large Scale Integr. Syst., 2022

Can Higher-Order Mutants Improve the Performance of Mutation-Based Fault Localization?
IEEE Trans. Reliab., 2022

Hardware Implementation of Hierarchical Temporal Memory Algorithm.
ACM J. Emerg. Technol. Comput. Syst., 2022

High Dimensional Optimization for Electronic Design.
Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

RxGAN: Modeling High-Speed Receiver through Generative Adversarial Networks.
Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

FAXID: FPGA-Accelerated XGBoost Inference for Data Centers using HLS.
Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022

2021
2Deep: Enhancing Side-Channel Attacks on Lattice-Based Key-Exchange via 2-D Deep Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

A Scalable Cluster-based Hierarchical Hardware Accelerator for a Cortically Inspired Algorithm.
ACM J. Emerg. Technol. Comput. Syst., 2021

Fast and Accurate PPA Modeling with Transfer Learning.
Proceedings of the 3rd ACM/IEEE Workshop on Machine Learning for CAD, 2021

Fast and Accurate PPA Modeling with Transfer Learning.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

A Review of 3D-Dynamic Random-Access Memory based Near-Memory Computation.
Proceedings of the IEEE International 3D Systems Integration Conference, 2021

Multi-ANN embedded system based on a custom 3D-DRAM.
Proceedings of the IEEE International 3D Systems Integration Conference, 2021

2020
Multi-Fidelity Surrogate-Based Optimization for Electromagnetic Simulation Acceleration.
ACM Trans. Design Autom. Electr. Syst., 2020

DeePar-SCA: Breaking Parallel Architectures of Lattice Cryptography via Learning Based Side-Channel Attacks.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020

Application of Quantum Machine Learning to VLSI Placement.
Proceedings of the MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD, 2020

Design Rule Checking with a CNN Based Feature Extractor.
Proceedings of the MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD, 2020

Machine Learning and Hardware security: Challenges and Opportunities -Invited Talk-.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019
Appliance Identification Algorithm for a Non-Intrusive Home Energy Monitor Using Cogent Confabulation.
IEEE Trans. Smart Grid, 2019

3-D-DATE: A Circuit-Level Three-Dimensional DRAM Area, Timing, and Energy Model.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Estimating Pareto Optimum Fronts to Determine Knob Settings in Electronic Design Automation Tools.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

An Application Specific Processor Architecture with 3D Integration for Recurrent Neural Networks.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

Improved Numerical Methodologies on Power System Dynamic Simulation Using GPU Implementation.
Proceedings of the IEEE Power & Energy Society Innovative Smart Grid Technologies Conference, 2019

Vertical Stack Thermal Characterization of Heterogeneous Integration and Packages.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2018
RF-Only Logic: an Area Efficient Logic Family for RF-Power Harvesting Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Exploring the Tradeoffs of Application-Specific Processing.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

2017
Corrections to "Crosstalk-Canceling Multimode Interconnect Using Transmitter Encoding".
IEEE Trans. Very Large Scale Integr. Syst., 2017

A robust calibration and supervised machine learning reliability framework for digitally-assisted self-healing RFICs.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

H3 (Heterogeneity in 3D): A Logic-on-Logic 3D-Stacked Heterogeneous Multi-Core Processor.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

2016
A Generally Applicable Calibration Algorithm for Digitally Reconfigurable Self-Healing RFICs.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Hardware implementation of Hierarchical Temporal Memory algorithm.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Design and ASIC acceleration of cortical algorithm for text recognition.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Design of a rectifier-free UHF Gen-2 compatible RFID Tag using RF-only logic.
Proceedings of the 2016 IEEE International Conference on RFID, 2016

Processor-in-memory support for artificial neural networks.
Proceedings of the IEEE International Conference on Rebooting Computing, 2016

Physical design of a 3D-stacked heterogeneous multi-core processor.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015
Under 100-cycle thread migration latency in a single-ISA heterogeneous multi-core processor.
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

Computing in 3D.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

Characterization of the mechanical stress impact on device electrical performance in the CMOS and III-V HEMT/HBT heterogeneous integration environment.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

Thermal simulation of heterogeneous GaN/ InP/silicon 3DIC stacks.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

Computing in 3D.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014
A Generic and Scalable Architecture for a Large Acoustic Model and Large Vocabulary Speech Recognition Accelerator Using Logic on Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Pathfinder3D: A framework for exploring early thermal tradeoffs in 3DIC.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

Leveraging 3D-IC for on-chip timing uncertainty measurements.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

Thermal effects of heterogeneous interconnects on InP / GaN / Si diverse integrated circuits.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

3D-enabled customizable embedded computer (3DECC).
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013
Crosstalk-Canceling Multimode Interconnect Using Transmitter Encoding.
IEEE Trans. Very Large Scale Integr. Syst., 2013

A Bounded and Discretized Nelder-Mead Algorithm Suitable for RFIC Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

MOOCs, OOCs, flips and hybrids: The new world of higher education.
Proceedings of the 2013 IEEE International Conference on Microelectronic Systems Education, 2013

Hetero<sup>2</sup> 3D integration: A scheme for optimizing efficiency/cost of Chip Multiprocessors.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Exploring early design tradeoffs in 3DIC.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Rationale for a 3D heterogeneous multi-core processor.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Face-to-face bus design with built-in self-test in 3D ICs.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

TSV-based, modular and collision detectable face-to-back shared bus design.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

Design of controller for L2 cache mapped in Tezzaron stacked DRAM.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

Design of 60 GHz contactless probe system for RDL in passive silicon interposer.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

Thermal requirements in future 3D processors.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012
Parallel Transient Simulation of Multiphysics Circuits Using Delay-Based Partitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Junction-Level Thermal Analysis of 3-D Integrated Circuits Using High Definition Power Blurring.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Dynamic electrothermal simulation of three-dimensional integrated circuits using standard cell macromodels.
IET Circuits Devices Syst., 2012

Comparing Through-Silicon-Via (TSV) Void/Pinhole Defect Self-Test Methods.
J. Electron. Test., 2012

Surrogate Model-Based Self-Calibrated Design for Process and Temperature Compensation in Analog/RF Circuits.
IEEE Des. Test, 2012

Simulation and Experimental Characterization of a Unified Memory Device with Two Floating-Gates.
Proceedings of the VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 2012

A novel double floating-gate unified memory device.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Process mismatch analysis based on reduced-order models.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

A 10.35 mW/GFlop stacked SAR DSP unit using fine-grain partitioned 3D integration.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
Design and Computer Aided Design of 3DIC.
Proceedings of the 3D Integration for NoC-based SoC Architectures, 2011

Reconfigurable five-layer three-dimensional integrated memory-on-logic synthetic aperture radar processor.
IET Comput. Digit. Tech., 2011

SPICE-compatible physical model of nanocrystal floating gate devices for circuit simulation.
IET Circuits Devices Syst., 2011

Computing with Novel Floating-Gate Devices.
Computer, 2011

Variation-Aware Circuit Macromodeling and Design Based on Surrogate Models.
Proceedings of the Simulation and Modeling Methodologies, Technologies and Applications, 2011

Application of Surrogate Modeling in Variation-aware Macromodel and Circuit Design.
Proceedings of the SIMULTECH 2011 - Proceedings of 1st International Conference on Simulation and Modeling Methodologies, Technologies and Applications, Noordwijkerhout, The Netherlands, 29, 2011

3D specific systems design and CAD.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Low power interconnect design for fpgas with bidirectional wiring using nanocrystal floating gate devices (abstract only).
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

Modeling and compare of through-silicon-via (TSV) in high frequency.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

Pathfinder 3D: A flow for system-level design space exploration.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

Coordinating 3D designs: Interface IP, standards or free form?
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010
Low-Power Hypercube Divided Memory FFT Engine Using 3D Integration.
ACM Trans. Design Autom. Electr. Syst., 2010

Creating 3D specific systems: Architecture, design and CAD.
Proceedings of the Design, Automation and Test in Europe, 2010

Logic-on-logic 3D integration and placement.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

The NCSU Tezzaron design kit.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

Thermal isolation in 3D chip stacks using vacuum gaps and capacitive or inductive communications.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009
A 32-Gb/s On-Chip Bus With Driver Pre-Emphasis Signaling.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Application Exploration for 3-D Integrated Circuits: TCAM, FIFO, and FFT Case Studies.
IEEE Trans. Very Large Scale Integr. Syst., 2009

A low power 3D integrated FFT engine using hypercube memory division.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Design automation for a 3DIC FFT processor for synthetic aperture radar: a case study.
Proceedings of the 46th Design Automation Conference, 2009

An enhanced macromodeling approach for differential output drivers.
Proceedings of the 2009 IEEE International Behavioral Modeling and Simulation Workshop, 2009

Through Silicon Via(TSV) defect/pinhole self test circuit for 3D-IC.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

Comparative analysis of two 3D integration implementations of a SAR processor.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

Technology impact analysis for 3D TCAM.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

Junction-level thermal extraction and simulation of 3DICs.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008
Editorial: Special issue on 3D integrated circuits and microarchitectures.
ACM J. Emerg. Technol. Comput. Syst., 2008

Keeping hot chips cool: are IC thermal problems hot air?
Proceedings of the 45th Design Automation Conference, 2008

Design and CAD for 3D integrated circuits.
Proceedings of the 45th Design Automation Conference, 2008

2007
Voltage-Mode Driver Preemphasis Technique For On-Chip Global Buses.
IEEE Trans. Very Large Scale Integr. Syst., 2007

SOI CMOS Implementation of a Multirate PSK Demodulator for Space Communications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

FreePDK: An Open-Source Variation-Aware Design Kit.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

Hardware Architecture of a Parallel Pattern Matching Engine.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Flexible Low Power Probability Density Estimation Unit For Speech Recognition.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Design Considerations and Benefits of Three-Dimensional Ternary Content Addressable Memory.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
3 gb/s AC coupled chip-to-chip communication using a low swing pulse receiver.
IEEE J. Solid State Circuits, 2006

Architecture for Low Power Large Vocabulary Speech Recognition.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Controlled nanowire fabrication by PEDAL process.
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

A 32Gb/s On-chip Bus with Driver Pre-emphasis Signaling.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

A 36Gb/s ACCI Multi-Channel Bus using a Fully Differential Pulse Receiver.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
Configurable string matching hardware for speeding up intrusion detection.
SIGARCH Comput. Archit. News, 2005

Demystifying 3D ICs: The Pros and Cons of Going Vertical.
IEEE Des. Test Comput., 2005

Molecular Electronics - Devices and Circuits Technology.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

Impact of an SoC Research Project on Microelectronics Education: A Case Study.
Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005

Driver pre-emphasis techniques for on-chip global buses.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

2004
The Design, Fabrication, and Characterization of Millimeter Scale Motors for Miniature Direct Drive Robots.
Proceedings of the 2004 IEEE International Conference on Robotics and Automation, 2004

Simplified delay design guidelines for on-chip global interconnects.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

The performance and experimental results of a multiple bit rate symbol timing recovery circuit for PSK receivers.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
Molecular electronics: from devices and interconnect to circuits and architecture.
Proc. IEEE, 2003

A low power PSK receiver for space applications in 0.35-μm SOI CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002
Novel hardware architecture for fast address lookups.
IEEE Commun. Mag., 2002

Binary search schemes for fast IP lookups.
Proceedings of the Global Telecommunications Conference, 2002

4 Gbps high-density AC coupled interconnection.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2001
Will Nanotechnology Change the Way We Design and Verify Systems? (Panel).
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

1999
The NCSU Cadence Design Kit for IC Fabrication through MOSIS.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 1999

Dynamically Programmable Cache Evaluation and Virtualization.
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

Parasitic Extraction Accuracy - How Much is Enough?
Proceedings of the 36th Conference on Design Automation, 1999

MEMS-Based Capacitor Arrays for Programmable Interconnect and RF Applications.
Proceedings of the 18th Conference on Advanced Research in VLSI (ARVLSI '99), 1999

1997
Clocking Optimization and Distribution in Digital Systems with Scheduled Skews.
J. VLSI Signal Process., 1997

Low power data processing by elimination of redundant computations.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

1995
Energy consumption modeling and optimization for SRAM's.
IEEE J. Solid State Circuits, May, 1995

Performance Driven Global Routing and Wiring Rule Generation for High Speed PCBs and MCMs.
Proceedings of the 32st Conference on Design Automation, 1995

1994
Energy control and accurate delay estimation in the design of CMOS buffers.
IEEE J. Solid State Circuits, September, 1994

Stochastic Optimization Approach to Transistor Sizing for CMOS VLSI Circuits.
Proceedings of the 31st Conference on Design Automation, 1994

1993
A Multichip Module Design Process for Notebook Computers.
Computer, 1993

System-Level Specification of Instruction Sets.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

A simple method for noise tolerance characterization of digital circuits.
Proceedings of the Third Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1993

1992
Tools to Aid in Wiring Rule Generation for High Speed Interconnects.
Proceedings of the 29th Design Automation Conference, 1992

An efficient table-driven decoder for one-half rate convolutional codes.
Proceedings of the 30th Annual Southeast Regional Conference, 1992

1990
Scalable VLSI implementations for neural networks.
J. VLSI Signal Process., 1990

1987
FIR digital filters for high sample rate applications.
IEEE Commun. Mag., 1987


  Loading...