Bharat L. Bhuva

According to our database¹, Bharat L. Bhuva authored at least 34 papers between 1989 and 2023.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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On csauthors.net:

Bibliography

2023

Soft Error Rate Predictions for Terrestrial Neutrons at the 3-nm Bulk FinFET Technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2023

Effects of Collected Charge and Drain Area on SE Response of SRAMs at the 5-nm FinFET Node.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2023

2022

Soft Error Characterization of D-FFs at the 5-nm Bulk FinFET Technology for the Terrestrial Environment.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2022

Single-Event Latchup Vulnerability at the 7-nm FinFET Node.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2022

2021

Frequency, LET, and Supply Voltage Dependence of Logic Soft Errors at the 7-nm Node.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2021

Scaling Trends in the Soft Error Rate of SRAMs from Planar to 5-nm FinFET.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2021

Effects of Temperature and Supply Voltage on Soft Errors for 7-nm Bulk FinFET Technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2021

2020

High-Current State triggered by Operating-Frequency Change.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Thermal Neutron Induced Soft Errors in 7-nm Bulk FinFET Node.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Temperature Dependence of Single-Event Transient Pulse Widths for 7-nm Bulk FinFET Technology.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

2019

Single-Event Upset Responses of Dual- and Triple-Well D Flip-Flop Designs in 7-nm Bulk FinFET Technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2019

Neutron Beam Attenuation Through Semiconductor Devices During SEU Testing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2019

Soft Error Performance of High-Speed Pulsed-DICE-Latch Design in 16 nm and 7 nm FinFET Processes.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2019

Alpha Particle Soft-Error Rates for D-FF Designs in 16-Nm and 7-Nm Bulk FinFET Technologies.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2019

2018

A TCAD evaluation of a single Bulk-BICS with integrative memory cell.

[BibT_eX]

[DOI]

Alexandre Simionovski

Gilson I. Wirth

Ronald D. Schrimpf

Bharat L. Bhuva

Microelectron. J., 2018

Evaluation on flip-flop physical unclonable functions in a 14/16-nm bulk FinFET technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2018

Single-event effects on optical transceiver.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2018

Designing soft-error-aware circuits with power and speed optimization.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2018

Impact of supply voltage and particle LET on the soft error rate of logic circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2018

2016

Single-event performance of differential flip-flop designs and hardening implication.

[BibT_eX]

[DOI]

Rongmei Chen

Enxia Zhang

Bharat L. Bhuva

Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

2015

Multi-cell soft errors at the 16-nm FinFET technology node.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2015

Influence of supply voltage on the multi-cell upset soft error sensitivity of dual- and triple-well 28 nm CMOS SRAMs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2015

Terrestrial SER characterization for nanoscale technologies: A comparative study.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2015

2014

Single-Event Transient Measurements on a DC/DC Pulse Width Modulator Using Heavy Ion, Proton, and Pulsed Laser.

[BibT_eX]

[DOI]

J. Electron. Test., 2014

2013

An efficient technique to select logic nodes for single event transient pulse-width reduction.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2013

A Bulk Built-In Voltage Sensor to Detect Physical Location of Single-Event Transients.

[BibT_eX]

[DOI]

Ramaswami Sammynaiken

J. Electron. Test., 2013

2012

Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Single-Event Effects Analysis of a Pulse Width Modulator IC in a DC/DC Converter.

[BibT_eX]

[DOI]

J. Electron. Test., 2012

2011

Impact of Synthesis Constraints on Error Propagation Probability of Digital Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Performance, metastability and soft-error robustness tradeoffs for flip-flops in 40nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2008

Design Technique for Mitigation of Soft Errors in Differential Switched-Capacitor Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2008

1993

Statistical degradation analysis of digital CMOS IC's.

[BibT_eX]

[DOI]

Venkata S. Rangavajjhala

Bharat L. Bhuva

Sherra E. Kerns

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

1992

Multi-level qualitative reasoning applied to CMOS digital circuits.

[BibT_eX]

[DOI]

Neeraj Kaul

Gautam Biswas

Bharat L. Bhuva

Artif. Intell. Eng., 1992

1989

Switch-level simulation of total dose effects on CMOS VLSI circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Bharat L. Bhuva

Timeline

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