John Niroula

According to our database1, John Niroula authored at least 7 papers between 2017 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2023
Towards DTCO in High Temperature GaN-on-Si Technology: Arithmetic Logic Unit at 300 °C and CAD Framework up to 500 °C.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

First Demonstration of GaN RF HEMTs on Engineered Substrate.
Proceedings of the Device Research Conference, 2023

2020
First Demonstration of GaN Vertical Power FinFETs on Engineered Substrate.
Proceedings of the 2020 Device Research Conference, 2020

Materials and Technology Issues for the Next Generation of Power Electronic Devices.
Proceedings of the 2020 Device Research Conference, 2020

2019
Using Floating Gate Memory to Train Ideal Accuracy Neural Networks.
CoRR, 2019

2018
Multiscale Co-Design Analysis of Energy, Latency, Area, and Accuracy of a ReRAM Analog Neural Training Accelerator.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

2017
Impact of Linearity and Write Noise of Analog Resistive Memory Devices in a Neural Algorithm Accelerator.
Proceedings of the IEEE International Conference on Rebooting Computing, 2017


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