Isaac Richter

According to our database, Isaac Richter authored at least 4 papers between 2016 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

DeTRAP: RISC-V Return Address Protection With Debug Triggers.

Isaac Richter, Jie Zhou, John Criswell

CoRR, 2024

DeTRAP: RISC-V Return Address Protection With Debug Triggers.

Isaac Richter, Jie Zhou, John Criswell

Proceedings of the IEEE Secure Development Conference, 2024

2018

Multiscale Co-Design Analysis of Energy, Latency, Area, and Accuracy of a ReRAM Analog Neural Training Accelerator.

Matthew J. Marinella, Sapan Agarwal, Alexander H. Hsia, Isaac Richter, Robin Jacobs-Gedrim, John Niroula, Steven J. Plimpton, Engin Ipek, Conrad D. James

IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

2016

Resistive memory device requirements for a neural algorithm accelerator.

Sapan Agarwal, Steven J. Plimpton, David R. Hughart, Alexander H. Hsia, Isaac Richter, Jonathan A. Cox, Conrad D. James, Matthew J. Marinella

Proceedings of the 2016 International Joint Conference on Neural Networks, 2016