Engin Ipek

Orcid: 0000-0003-2809-5809

Affiliations:
  • Microsoft Research


According to our database1, Engin Ipek authored at least 51 papers between 2005 and 2024.

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Bibliography

2024
TCAM-SSD: A Framework for Search-Based Computing in Solid-State Drives.
CoRR, 2024

2021
An Analog Preconditioner for Solving Linear Systems.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

2020
Adapting In Situ Accelerators for Sparsity with Granular Matrix Reordering.
IEEE Comput. Archit. Lett., 2020

Commutative Data Reordering: A New Technique to Reduce Data Movement Energy on Sparse Inference Workloads.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

2019
Content Aware Refresh: Exploiting the Asymmetry of DRAM Retention Errors to Reduce the Refresh Frequency of Less Vulnerable Data.
IEEE Trans. Computers, 2019

Memristive Accelerators for Dense and Sparse Linear Algebra: From Machine Learning to High-Performance Scientific Computing.
IEEE Micro, 2019

2018
Sanitizer: Mitigating the Impact of Expensive ECC Checks on STT-MRAM Based Main Memories.
IEEE Trans. Computers, 2018

Multiscale Co-Design Analysis of Energy, Latency, Area, and Accuracy of a ReRAM Analog Neural Training Accelerator.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Vertical Writes: Closing the Throughput Gap between Deeply Scaled STT-MRAM and DRAM.
IEEE Comput. Archit. Lett., 2018

Bit-Level Load Balancing: A New Technique for Improving the Write Throughput of Deeply Scaled STT-MRAM.
IEEE Comput. Archit. Lett., 2018

Enabling Scientific Computing on Memristive Accelerators.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Making Memristive Neural Network Accelerators Reliable.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017
The Memristive Boltzmann Machines.
IEEE Micro, 2017

Voltage Regulator Efficiency Aware Power Management.
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

2016
Reducing Switching Latency and Energy in STT-MRAM Caches With Field-Assisted Writing.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Reducing data movement energy via online data clustering and encoding.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Memristive Boltzmann machine: A hardware accelerator for combinatorial optimization and deep learning.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

2015
Energy-Efficient Nonvolatile Flip-Flop With Subnanosecond Data Backup Time for Fine-Grain Power Gating.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Resistive Ternary Content Addressable Memory Systems for Data-Intensive Computing.
IEEE Micro, 2015

More is less: improving the energy efficiency of data movement via opportunistic use of sparse codes.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

Enabling energy efficient Hybrid Memory Cube systems with erasure codes.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Energy-efficient data movement with sparse transition encoding.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Architecting a MOS current mode logic (MCML) processor for fast, low noise and energy-efficient computing in the near-threshold regime.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

2014
2T-1R STT-MRAM memory cells for enhanced on/off current ratio.
Microelectron. J., 2014

Field driven STT-MRAM cell for reduced switching latency and energy.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
A programmable memory controller for the DDRx interfacing standards.
ACM Trans. Comput. Syst., 2013

Programmable DDRx Controllers.
IEEE Micro, 2013

DESC: energy-efficient data exchange using synchronized counters.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

AC-DIMM: associative computing with STT-MRAM.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

2012
STT-MRAM memory cells with enhanced on/off ratio.
Proceedings of the IEEE 25th International SOC Conference, 2012

PARDIS: A programmable memory controller for the DDRx interfacing standards.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

Overcoming single-thread performance hurdles in the core fusion reconfigurable multicore architecture.
Proceedings of the International Conference on Supercomputing, 2012

2011
A resistive TCAM accelerator for data-intensive computing.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

2010
Phase-Change Technology and the Future of Main Memory.
IEEE Micro, 2010

Phase change memory architecture and the quest for scalability.
Commun. ACM, 2010

Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

Dynamically replicated memory: building reliable systems from nanoscale resistive memories.
Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, 2010

2009
Dynamic Multicore Resource Management: A Machine Learning Approach.
IEEE Micro, 2009

Better I/O through byte-addressable, persistent memory.
Proceedings of the 22nd ACM Symposium on Operating Systems Principles 2009, 2009

Architecting phase change memory as a scalable dram alternative.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

2008
Efficient architectural design space exploration via predictive modeling.
ACM Trans. Archit. Code Optim., 2008

Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach.
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

Self-Optimizing Memory Controllers: A Reinforcement Learning Approach.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

2007
Predicting parallel application performance via machine learning approaches.
Concurr. Comput. Pract. Exp., 2007

Core fusion: accommodating software diversity in chip multiprocessors.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

A Reconfigurable Chip Multiprocessor Architecture to Accommodate Software Diversity.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor.
Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2007

2006
Dynamic program phase detection in distributed shared-memory multiprocessors.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Efficiently exploring architectural design spaces via predictive modeling.
Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, 2006

2005
An Approach to Performance Prediction for Parallel Applications.
Proceedings of the Euro-Par 2005, Parallel Processing, 11th International Euro-Par Conference, Lisbon, Portugal, August 30, 2005


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