Paul J. Hurst

According to our database1, Paul J. Hurst authored at least 51 papers between 1988 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2020
A Two-Step ADC With Statistical Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

2019
Digital Background Calibration of a Split Current-Steering DAC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018
Design of a Wideband Bandpass Stacked HBT Distributed Amplifier in InP.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2016
Iterative Gain Enhancement in an Algorithmic ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

An algorithmic ADC with greater than rail-to-rail input range and near-Vt supply.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
An Integrator-Based Pipelined ADC With Digital Calibration.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

2014
Background Adaptive Cancellation of Digital Switching Noise in a Pipelined Analog-to-Digital Converter Without Noise Sensors.
IEEE J. Solid State Circuits, 2014

2013
Immediate Calibration of Operational Amplifier Gain Error in Pipelined ADCs Using Extended Correlated Double Sampling.
IEEE J. Solid State Circuits, 2013

2012
Canceling the ISI Due to Finite S/H Bandwidth in a Circular Buffer Forward Equalizer.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

Overcoming the Effect of the Summation-Node Parasitic Pole in an Analog Equalizer.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Correcting the Effects of Mismatches in Time-Interleaved Analog Adaptive FIR Equalizers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A Pipelined ADC With Metastability Error Rate <10<sup>-15</sup> Errors/Sample.
IEEE J. Solid State Circuits, 2012

Background adaptive cancellation of digital switching noise in pipelined ADCs without noise sensors.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
A Digitally Corrected 5-mW 2-MS/s SC Delta Sigma ADC in 0.25- μ m CMOS With 94-dB SFDR.
IEEE J. Solid State Circuits, 2011

2010
A Four-Channel Time-Interleaved ADC With Digital Calibration of Interchannel Timing and Memory Errors.
IEEE J. Solid State Circuits, 2010

Highly programmable switched-capacitor filters using biquads with nonuniform internal clocks.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Calibration of pipelined ADC gain and memory errors in an adaptively equalized receiver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A parametric polyphase domain approach to blind calibration of timing mismatches for M-channel time-interleaved ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A digitally calibrated 5-mW 2-MS/s 4th-order ΔΣ ADC in 0.25-μm CMOS with 94 dB SFDR.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009
Gain-Error Calibration of a Pipelined ADC in an Adaptively Equalized Baseband Receiver.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

A Level-Crossing Analog-to-Digital Converter With Triangular Dither.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Correction of Mismatches in a Time-Interleaved Analog-to-Digital Converter in an Adaptively Equalized Digital Communication Receiver.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Adaptive Semiblind Calibration of Bandwidth Mismatch for Two-Channel Time-Interleaved ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Digital Calibration of a Nonlinear S/H.
IEEE J. Sel. Top. Signal Process., 2009

Nested Digital Background Calibration of a 12-bit Pipelined ADC Without an Input SHA.
IEEE J. Solid State Circuits, 2009

A Full-Wave Rectifier With Integrated Peak Selection for Multiple Electrode Piezoelectric Energy Harvesters.
IEEE J. Solid State Circuits, 2009

An energy-aware multiple-input power supply with charge recovery for energy harvesting applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
DAC Quantization-Noise Cancellation in an Echo-Canceling Transceiver.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

A Programmable Impedance Matching Circuit for Voiceband Modems.
IEEE J. Solid State Circuits, 2008

A Full-Wave Rectifier for Interfacing with Multi-Phase Piezoelectric Energy Harvesters.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
A Passive Switched-Capacitor Finite-Impulse-Response Equalizer.
IEEE J. Solid State Circuits, 2007

Bandwidth Mismatch Correction for a Two-Channel Time-Interleaved A/D Converter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Bandwidth Mismatch and Its Correction in Time-Interleaved Analog-to-Digital Converters.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

Digital background calibration for memory effects in pipelined analog-to-digital converters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Effect of nonlinearity in the CMFB circuit that uses the differential-difference amplifier.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Background interstage gain calibration technique for pipelined ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Correction to "Calibration of Sample-Time Error in a Two-Channel Time-Interleaved Analog-to-Digital Converter".
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Convergence analysis of a background interstage gain calibration technique for pipelined ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A 200 MS/s passive switched-capacitor FIR equalizer using a time-interleaved topology.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
A mixed-signal approach for tuning continuous-time low-pass filters.
IEEE Trans. Circuits Syst. II Express Briefs, 2004

Reconstruction of band-limited periodic nonuniformly sampled signals through multirate filter banks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Calibration of sample-time error in a two-channel time-interleaved analog-to-digital converter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

2001
A mixed-signal tuning approach for continuous-time LPFs.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

1994
A Comparison of Analog DFE Architectures for Disk-Drive Applications.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1992
A VLSI processor for parallel contour tracing.
IEEE Trans. Signal Process., 1992

High-speed computation of the Radon transform and backprojection using an expandable multiprocessor architecture.
IEEE Trans. Circuits Syst. Video Technol., 1992

1990
An evaluation of Radon transform computations using DSP chips.
Mach. Vis. Appl., 1990

A VLSI architecture for two-dimensional Radon transform computations.
Proceedings of the 1990 International Conference on Acoustics, 1990

1989
A Radon transform computer for multidimensional signal processing.
Proceedings of the IEEE International Conference on Acoustics, 1989

1988
An expandable VLSI processor array approach to contour tracing.
Proceedings of the IEEE International Conference on Acoustics, 1988


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