Stephen H. Lewis

According to our database1, Stephen H. Lewis authored at least 32 papers between 2004 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
A Two-Step ADC With Statistical Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

2019
Digital Background Calibration of a Split Current-Steering DAC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2016
Iterative Gain Enhancement in an Algorithmic ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

An algorithmic ADC with greater than rail-to-rail input range and near-Vt supply.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
An Integrator-Based Pipelined ADC With Digital Calibration.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

2014
Background Adaptive Cancellation of Digital Switching Noise in a Pipelined Analog-to-Digital Converter Without Noise Sensors.
IEEE J. Solid State Circuits, 2014

2013
Immediate Calibration of Operational Amplifier Gain Error in Pipelined ADCs Using Extended Correlated Double Sampling.
IEEE J. Solid State Circuits, 2013

2012
A Pipelined ADC With Metastability Error Rate <10<sup>-15</sup> Errors/Sample.
IEEE J. Solid State Circuits, 2012

Background adaptive cancellation of digital switching noise in pipelined ADCs without noise sensors.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
A Digitally Corrected 5-mW 2-MS/s SC Delta Sigma ADC in 0.25- μ m CMOS With 94-dB SFDR.
IEEE J. Solid State Circuits, 2011

2010
Prediction of the Spectrum of a Digital Delta-Sigma Modulator Followed by a Polynomial Nonlinearity.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A Four-Channel Time-Interleaved ADC With Digital Calibration of Interchannel Timing and Memory Errors.
IEEE J. Solid State Circuits, 2010

Highly programmable switched-capacitor filters using biquads with nonuniform internal clocks.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Calibration of pipelined ADC gain and memory errors in an adaptively equalized receiver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A digitally calibrated 5-mW 2-MS/s 4th-order ΔΣ ADC in 0.25-μm CMOS with 94 dB SFDR.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009
Gain-Error Calibration of a Pipelined ADC in an Adaptively Equalized Baseband Receiver.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

Self-Biased Unity-Gain Buffers With Low Gain Error.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

A Level-Crossing Analog-to-Digital Converter With Triangular Dither.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Correction of Mismatches in a Time-Interleaved Analog-to-Digital Converter in an Adaptively Equalized Digital Communication Receiver.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Nested Digital Background Calibration of a 12-bit Pipelined ADC Without an Input SHA.
IEEE J. Solid State Circuits, 2009

An energy-aware multiple-input power supply with charge recovery for energy harvesting applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2007
A 1.4 V Supply CMOS Fractional Bandgap Reference.
IEEE J. Solid State Circuits, 2007

A Passive Switched-Capacitor Finite-Impulse-Response Equalizer.
IEEE J. Solid State Circuits, 2007

2006
Bandwidth Mismatch and Its Correction in Time-Interleaved Analog-to-Digital Converters.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

Digital background calibration for memory effects in pipelined analog-to-digital converters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

A Unity-Gain Buffer with Reduced Offset and Gain Error.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
Background interstage gain calibration technique for pipelined ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Correction to "Calibration of Sample-Time Error in a Two-Channel Time-Interleaved Analog-to-Digital Converter".
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Convergence analysis of a background interstage gain calibration technique for pipelined ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A 200 MS/s passive switched-capacitor FIR equalizer using a time-interleaved topology.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
Calibration of sample-time error in a two-channel time-interleaved analog-to-digital converter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004


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