Jonathan W. Greene

According to our database, Jonathan W. Greene authored at least 15 papers between 1984 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Accounting for Floorplan Irregularity and Configuration Dependence in FPGA Routing Delay Models.

Gabriel Barajas, Jonathan W. Greene, Fei Li, James Tandon

Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

FPGA Mux Usage and Routability Estimates without Explicit Routing.

Jonathan W. Greene

Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

Narrowing the Synthesis Gap: Academic FPGA Synthesis is Catching Up With the Industry.

Benjamin Lukas Cajus Barzen, Arya Reais-Parsi, Eddie Hung, Minwoo Kang, Alan Mishchenko, Jonathan W. Greene, John Wawrzynek

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2018

Improving FPGA Performance with a S44 LUT Structure.

Wenyi Feng, Jonathan W. Greene, Alan Mishchenko

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2015

Technology Mapping into General Programmable Cells.

Alan Mishchenko, Robert K. Brayton, Wenyi Feng, Jonathan W. Greene

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

2014

Rent's rule based FPGA packing for routability optimization.

Wenyi Feng, Jonathan W. Greene, Kristofer Vorwerk, Val Pevzner, Arun Kundu

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

2011

A 65nm flash-based FPGA fabric optimized for low cost and power.

Jonathan W. Greene, Sinan Kaptanoglu, Wenyi Feng, Volker Hecht, Joel Landry, Fei Li, Anton Krouglyanskiy, Mihai Morosan, Val Pevzner

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2009

Improving Simulated Annealing-Based FPGA Placement With Directed Moves.

Kristofer Vorwerk, Andrew A. Kennings, Jonathan W. Greene

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

2007

Improving Annealing Via Directed Moves.

Kristofer Vorwerk, Andrew A. Kennings, Jonathan W. Greene, Doris T. Chen

Proceedings of the FPL 2007, 2007

2006

Post-placement interconnect entropy: how many configuration bits does a programmable logic device need?

Wenyi Feng, Jonathan W. Greene

Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006

Post-placement interconnect entropy.

Wenyi Feng, Jonathan W. Greene

Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

1993

Segmented channel routing.

Vwani P. Roychowdhury, Jonathan W. Greene, Abbas El Gamal

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

1990

Segmented Channel Routing.

Jonathan W. Greene, Vwani P. Roychowdhury, Sinan Kaptanoglu, Abbas El Gamal

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989

An architecture for electrically configurable gate arrays.

Abbas El Gamal, Jonathan W. Greene, Justin Reyneri, Eric Rogoyski, Khaled A. El-Ayat, Amr Mohsen

IEEE J. Solid State Circuits, April, 1989

1984

Configuration of VLSI Arrays in the Presence of Defects.

Jonathan W. Greene, Abbas El Gamal

J. ACM, 1984