John Wawrzynek

According to our database, John Wawrzynek authored at least 112 papers between 1984 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

SPADES: A Productive Design Flow for Versal Programmable Logic.

Tan Nguyen, Zachary Blair, Stephen Neuendorffer, John Wawrzynek

Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

Narrowing the Synthesis Gap: Academic FPGA Synthesis is Catching Up With the Industry.

Benjamin Lukas Cajus Barzen, Arya Reais-Parsi, Eddie Hung, Minwoo Kang, Alan Mishchenko, Jonathan W. Greene, John Wawrzynek

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

Learning A Continuous and Reconstructible Latent Space for Hardware Accelerator Design.

Qijing Huang, Charles Hong, John Wawrzynek, Mahesh Subedar, Yakun Sophia Shao

Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022

2021

CoSA: Scheduling by Constrained Optimization for Spatial Accelerators.

Qijing Huang, Aravind Kalaiah, Minwoo Kang, James Demmel, Grace Dinh, John Wawrzynek, Thomas Norell, Yakun Sophia Shao

Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

CoDeNet: Efficient Deployment of Input-Adaptive Object Detection on Embedded FPGAs.

Qijing Huang, Dequan Wang, Zhen Dong, Yizhao Gao, Yaohui Cai, Tian Li, Bichen Wu, Kurt Keutzer, John Wawrzynek

Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

HAO: Hardware-aware Neural Architecture Optimization for Efficient Inference.

Zhen Dong, Yizhao Gao, Qijing Huang, John Wawrzynek, Hayden K. H. So, Kurt Keutzer

Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

2020

CoDeNet: Algorithm-hardware Co-design for Deformable Convolution.

Zhen Dong, Dequan Wang, Qijing Huang, Yizhao Gao, Yaohui Cai, Bichen Wu, Kurt Keutzer, John Wawrzynek

CoRR, 2020

ProTuner: Tuning Programs with Monte Carlo Tree Search.

Ameer Haj-Ali, Hasan Genc, Qijing Huang, William S. Moses, John Wawrzynek, Krste Asanovic, Ion Stoica

CoRR, 2020

SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays.

Yukio Miyasaka, Masahiro Fujita, Alan Mishchenko, John Wawrzynek

Proceedings of the VLSI-SoC: Design Trends, 2020

AutoPhase: Juggling HLS Phase Orderings in Random Forests with Deep Reinforcement Learning.

Ameer Haj-Ali, Qijing (Jenny) Huang, William S. Moses, John Xiang, Krste Asanovic, John Wawrzynek, Ion Stoica

Proceedings of Machine Learning and Systems 2020, 2020

2019

HyVE: Hybrid Vertex-Edge Memory Hierarchy for Energy-Efficient Graph Processing.

Guohao Dai, Tianhao Huang, Yu Wang, Huazhong Yang, John Wawrzynek

IEEE Trans. Computers, 2019

AutoPhase: Compiler Phase-Ordering for High Level Synthesis with Deep Reinforcement Learning.

Ameer Haj Ali, Qijing Huang, William S. Moses, John Xiang, Ion Stoica, Krste Asanovic, John Wawrzynek

CoRR, 2019

Antenna Array Geometries for Directional Wireless Networks.

James C. Martin, Robert W. Brodersen, John Wawrzynek

Proceedings of the 2019 IEEE Wireless Communications and Networking Conference, 2019

Algorithm-hardware Co-design for Deformable Convolution.

Qijing Huang, Dequan Wang, Yizhao Gao, Yaohui Cai, Zhen Dong, Bichen Wu, Kurt Keutzer, John Wawrzynek

Proceedings of the Fifth Workshop on Energy Efficient Machine Learning and Cognitive Computing, 2019

Centrifuge: Evaluating full-system HLS-generated heterogenous-accelerator SoCs using FPGA-Acceleration.

Qijing Huang, Christopher Yarp, Sagar Karandikar, Nathan Pemberton, Benjamin Brock, Liang Ma, Guohao Dai, Robert Quitt, Krste Asanovic, John Wawrzynek

Proceedings of the International Conference on Computer-Aided Design, 2019

Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs.

Yifan Yang, Qijing Huang, Bichen Wu, Tianjun Zhang, Liang Ma, Giulio Gambardella, Michaela Blott, Luciano Lavagno, Kees A. Vissers, John Wawrzynek, Kurt Keutzer

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

AutoPhase: Compiler Phase-Ordering for HLS with Deep Reinforcement Learning.

Qijing Huang, Ameer Haj-Ali, William S. Moses, John Xiang, Ion Stoica, Krste Asanovic, John Wawrzynek

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

GraphSAR: a sparsity-aware processing-in-memory architecture for large-scale graph processing on ReRAMs.

Guohao Dai, Tianhao Huang, Yu Wang, Huazhong Yang, John Wawrzynek

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

AWStream: adaptive wide-area streaming analytics.

Ben Zhang, Xin Jin, Sylvia Ratnasamy, John Wawrzynek, Edward A. Lee

Proceedings of the 2018 Conference of the ACM Special Interest Group on Data Communication, 2018

Receiver Adaptive Beamforming and Interference of Indoor Environments in mmWave.

James C. Martin, Robert W. Brodersen, John Wawrzynek

Proceedings of the 29th IEEE Annual International Symposium on Personal, 2018

NewGraph: Balanced Large-Scale Graph Processing on FPGAs with Low Preprocessing Overheads.

Guohao Dai, Tianhao Huang, Yu Wang, Huazhong Yang, John Wawrzynek

Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

2017

Proceedings of the 3rd International Workshop on Overlay Architectures for FPGAs (OLAF 2017).

Hayden Kwok-Hay So, John Wawrzynek

CoRR, 2017

SLSR: A flexible middleware localization service architecture.

Filip Lemic, Vlado Handziski, Ivan Azcarate, John Wawrzynek, Jan M. Rabaey, Adam Wolisz

Proceedings of the 2017 International Conference on Indoor Positioning and Indoor Navigation, 2017

Selection and Aggregation of Location Information Provisioning Services.

Filip Lemic, Vlado Handziski, Mladen Miksa, Jan M. Rabaey, John Wawrzynek, Adam Wolisz

Proceedings of the 26th International Conference on Computer Communication and Networks, 2017

Synthesis of program binaries into FPGA accelerators with runtime dependence validation.

Shaoyi Cheng, Qijing Huang, John Wawrzynek

Proceedings of the International Conference on Field Programmable Technology, 2017

OLAF'17: Third International Workshop on Overlay Architectures for FPGAs.

Hayden Kwok-Hay So, John Wawrzynek

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

Compressive sensing and sparse antenna arrays for indoor 3-D microwave imaging.

Simon Scott, John Wawrzynek

Proceedings of the 25th European Signal Processing Conference, 2017

2016

Toward a Global Data Infrastructure.

Nitesh Mor, Ben Zhang, John Kolb, Douglas S. Chan, Nikhil Goyal, Nicholas Sun, Ken Lutz, Eric Allman, John Wawrzynek, Edward A. Lee, John Kubiatowicz

IEEE Internet Comput., 2016

Proceedings of the 2nd International Workshop on Overlay Architectures for FPGAs (OLAF 2016).

Hayden Kwok-Hay So, John Wawrzynek

CoRR, 2016

High Level Synthesis with a Dataflow Architectural Template.

Shaoyi Cheng, John Wawrzynek

CoRR, 2016

Localization as a feature of mmWave communication.

Filip Lemic, James C. Martin, Christopher Yarp, Douglas S. Chan, Vlado Handziski, Robert W. Brodersen, Gerhard P. Fettweis, Adam Wolisz, John Wawrzynek

Proceedings of the 2016 International Wireless Communications and Mobile Computing Conference (IWCMC), 2016

Toward standardized localization service.

Filip Lemic, Vlado Handziski, Nitesh Mor, Jan M. Rabaey, John Wawrzynek, Adam Wolisz

Proceedings of the International Conference on Indoor Positioning and Indoor Navigation, 2016

Synthesis of statically analyzable accelerator networks from sequential programs.

Shaoyi Cheng, John Wawrzynek

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

OLAF'16: Second International Workshop on Overlay Architectures for FPGAs.

Hayden Kwok-Hay So, John Wawrzynek

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2015

ASTRO: Synthesizing application-specific reconfigurable hardware traces to exploit memory-level parallelism.

Mingjie Lin, Shaoyi Cheng, Ronald F. DeMara, John Wawrzynek

Microprocess. Microsystems, 2015

The Cloud is Not Enough: Saving IoT from the Cloud.

Ben Zhang, Nitesh Mor, John Kolb, Douglas S. Chan, Ken Lutz, Eric Allman, John Wawrzynek, Edward A. Lee, John Kubiatowicz

Proceedings of the 7th USENIX Workshop on Hot Topics in Cloud Computing, 2015

2014

The Swarm at the Edge of the Cloud.

Edward A. Lee, Björn Hartmann, John Kubiatowicz, Tajana Simunic Rosing, John Wawrzynek, David Wessel, Jan M. Rabaey, Kris Pister, Alberto L. Sangiovanni-Vincentelli, Sanjit A. Seshia, David T. Blaauw, Prabal Dutta, Kevin Fu, Carlos Guestrin, Ben Taskar, Roozbeh Jafari, Douglas L. Jones, Vijay Kumar, Rahul Mangharam, George J. Pappas, Richard M. Murray, Anthony Rowe

IEEE Des. Test, 2014

Architectural synthesis of computational pipelines with decoupled memory access.

Shaoyi Cheng, John Wawrzynek

Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

2013

Extracting memory-level parallelism through reconfigurable hardware traces.

Mingjie Lin, Shaoyi Cheng, John Wawrzynek

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Reconfigurable computing in the era of post-silicon scaling [panel discussion].

Eric S. Chung, Doug Burger, Mike Butts, Jan Gray, Chuck Thacker, Kees A. Vissers, John Wawrzynek

Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

2012

Selectively Fortifying Reconfigurable Computing Device to Achieve Higher Error Resilience.

Mingjie Lin, Yu Bai, John Wawrzynek

J. Electr. Comput. Eng., 2012

Exploring Many-Core Design Templates for FPGAs and ASICs.

Ilia A. Lebedev, Christopher W. Fletcher, Shaoyi Cheng, James C. Martin, Austin Doupnik, Daniel Burke, Mingjie Lin, John Wawrzynek

Int. J. Reconfigurable Comput., 2012

Exploiting Memory-Level Parallelism in Reconfigurable Accelerators.

Shaoyi Cheng, Mingjie Lin, Hao Jun Liu, Simon Scott, John Wawrzynek

Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

Chisel: constructing hardware in a Scala embedded language.

Jonathan Bachrach, Huy Vo, Brian C. Richards, Yunsup Lee, Andrew Waterman, Rimas Avizienis, John Wawrzynek, Krste Asanovic

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011

Discriminatively Fortified Computing with Reconfigurable Digital Fabric.

Mingjie Lin, Yu Bai, John Wawrzynek

Proceedings of the 13th IEEE International Symposium on High-Assurance Systems Engineering, 2011

Should the academic community launch an open-source FPGA device and tools effort?: evening panel.

John Wawrzynek

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

Using many-core architectural templates for FPGA-based computing (abstract only).

Mingjie Lin, Shaoyi Cheng, John Wawrzynek

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

Bridging the GPGPU-FPGA efficiency gap.

Christopher W. Fletcher, Ilia A. Lebedev, Narges Bani Asadi, Daniel Burke, John Wawrzynek

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

Advances and challenges of computing with FPGAs.

John Wawrzynek

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010

Exploring FPGA Routing Architecture Stochastically.

Mingjie Lin, John Wawrzynek, Abbas El Gamal

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Improving FPGA Placement With Dynamically Adaptive Stochastic Tunneling.

Mingjie Lin, John Wawrzynek

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Cascading Deep Pipelines to Achieve High Throughput in Numerical Reduction Operations.

Mingjie Lin, Shaoyi Cheng, John Wawrzynek

Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

MARC: A Many-Core Approach to Reconfigurable Computing.

Ilia A. Lebedev, Shaoyi Cheng, Austin Doupnik, James C. Martin, Christopher W. Fletcher, Daniel Burke, Mingjie Lin, John Wawrzynek

Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

<i>ParaLearn</i>: a massively parallel, scalable system for learning interaction networks on FPGAs.

Narges Bani Asadi, Christopher W. Fletcher, Greg Gibeling, John Wawrzynek, Wing H. Wong, Garry P. Nolan

Proceedings of the 24th International Conference on Supercomputing, 2010

OpenRCL: Low-Power High-Performance Computing with Reconfigurable Devices.

Mingjie Lin, Ilia A. Lebedev, John Wawrzynek

Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

High-throughput bayesian computing machine with reconfigurable hardware.

Mingjie Lin, Ilia A. Lebedev, John Wawrzynek

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

2009

A view of the parallel computing landscape.

Krste Asanovic, Rastislav Bodík, James Demmel, Tony M. Keaveny, Kurt Keutzer, John Kubiatowicz, Nelson Morgan, David A. Patterson, Koushik Sen, John Wawrzynek, David Wessel, Katherine A. Yelick

Commun. ACM, 2009

A design methodology for domain-optimized power-efficient supercomputing.

Marghoob Mohiyuddin, Mark Murphy, Leonid Oliker, John Shalf, John Wawrzynek, Samuel Williams

Proceedings of the ACM/IEEE Conference on High Performance Computing, 2009

Using adaptive routing to compensate for performance heterogeneity.

Yury Markovsky, Yatish Patel, John Wawrzynek

Proceedings of the Third International Symposium on Networks-on-Chips, 2009

2008

Workloads of the Future.

Jan M. Rabaey, Daniel Burke, Ken Lutz, John Wawrzynek

IEEE Des. Test Comput., 2008

2007

RAMP: Research Accelerator for Multiple Processors.

John Wawrzynek, David A. Patterson, Mark Oskin, Shih-Lien Lu, Christoforos E. Kozyrakis, James C. Hoe, Derek Chiou, Krste Asanovic

IEEE Micro, 2007

Adventures with a Reconfigurable Research Platform.

John Wawrzynek

Proceedings of the FPL 2007, 2007

RAMP Blue: A Message-Passing Manycore System in FPGAs.

Alex Krasnov, Andrew Schultz, John Wawrzynek, Greg Gibeling, Pierre-Yves Droz

Proceedings of the FPL 2007, 2007

2006

An Implementation Guide for RTP MIDI.

John Lazzaro, John Wawrzynek

RFC, November, 2006

RTP Payload Format for MIDI.

John Lazzaro, John Wawrzynek

RFC, November, 2006

Stream computations organized for reconfigurable execution.

André DeHon, Yury Markovsky, Eylon Caspi, Michael Chu, Randy Huang, Stylianos Perissakis, Laura Pozzi, Joseph Yeh, John Wawrzynek

Microprocess. Microsystems, 2006

Stochastic spatial routing for reconfigurable networks.

André DeHon, Randy Huang, John Wawrzynek

Microprocess. Microsystems, 2006

Research accelerator for multiple processors.

David A. Patterson, Arvind, Krste Asanovic, Derek Chiou, James C. Hoe, Christos Kozyrakis, Shih-Lien Lu, Mark Oskin, Jan M. Rabaey, John Wawrzynek

Proceedings of the 2006 IEEE Hot Chips 18 Symposium (HCS), 2006

2005

BEE2: A High-End Reconfigurable Computing System.

Chen Chang, John Wawrzynek, Robert W. Brodersen

IEEE Des. Test Comput., 2005

Defect Tolerance in Multiple-FPGA Systems.

Zohair Hyder, John Wawrzynek

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

The Design And Application Of A High-End Reconfigurable Computing System.

Chen Chang, John Wawrzynek, Pierre-Yves Droz, Robert W. Brodersen

Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005

2004

The SFRA: a corner-turn FPGA architecture.

Nicholas Weaver, John R. Hauser, John Wawrzynek

Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

2003

Guest Editors' Introduction: Hot Chips 14 - Innovation in the Face of Uncertain Economics.

John Wawrzynek, Keith Diefendorff

IEEE Micro, 2003

Quality based compute-resource allocation in real-time signal processing.

Joseph Yeh, John Wawrzynek

Proceedings of the 2003 IEEE International Conference on Acoustics, 2003

Post-placement C-slow retiming for the xilinx virtex FPGA.

Nicholas Weaver, Yury Markovsky, Yatish Patel, John Wawrzynek

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

Stochastic, spatial routing for hypergraphs, trees, and meshes.

Randy Huang, John Wawrzynek, André DeHon

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

2002

Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine.

Yury Markovsky, Eylon Caspi, Randy Huang, Joseph Yeh, Michael Chu, John Wawrzynek, André DeHon

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002

The Effects of Datapath Placement and C-Slow Retiming on Three Computational Benchmarks.

Nicholas Weaver, John Wawrzynek

Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

Hardware-Assisted Fast Routing.

André DeHon, Randy Huang, John Wawrzynek

Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

2001

A case for network musical performance.

John Lazzaro, John Wawrzynek

Proceedings of the Network and Operating System Support for Digital Audio and Video, 2001

2000

The Garp Architecture and C Compiler.

Timothy J. Callahan, John R. Hauser, John Wawrzynek

Computer, 2000

Stream Computations Organized for Reconfigurable Execution (SCORE).

Eylon Caspi, Michael Chu, Randy Huang, Joseph Yeh, John Wawrzynek, André DeHon

Proceedings of the Field-Programmable Logic and Applications, 2000

Adapting software pipelining for reconfigurable computing.

Timothy J. Callahan, John Wawrzynek

Proceedings of the 2000 International Conference on Compilers, 2000

A Comparison of the AES Candidates Amenability to FPGA Implementation.

Nicholas Weaver, John Wawrzynek

Proceedings of the Third Advanced Encryption Standard Candidate Conference, 2000

1999

JPEG Quality Transcoding Using Neural Networks Trained With a Perceptual Error Measure.

John Lazzaro, John Wawrzynek

Neural Comput., 1999

Real products, real technology Guest Editor's Introduction].

Norman P. Jouppi, John Wawrzynek

IEEE Micro, 1999

A fixed-point recursive digital oscillator for additive synthesis of audio.

Todd D. Hodes, John R. Hauser, John Wawrzynek, Adrian Freed, David Wessel

Proceedings of the 1999 IEEE International Conference on Acoustics, 1999

HSRA: High-Speed, Hierarchical Synchroous Reconfigurable Array.

William Tsu, Kip Macy, Atul Joshi, Randy Huang, Norman Walker, Tony Tung, Omid Rowhani, George Varghese, John Wawrzynek, André DeHon

Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

Reconfigurable Computing: What, Why, and Implications for Design Automation.

André DeHon, John Wawrzynek

Proceedings of the 36th Conference on Design Automation, 1999

1998

Instruction-Level Parallelism for Reconfigurable Computing.

Timothy J. Callahan, John Wawrzynek

Proceedings of the Field-Programmable Logic and Applications, 1998

Fast Module Mapping and Placement for Datapaths in FPGAs.

Timothy J. Callahan, Philip Chong, André DeHon, John Wawrzynek

Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

Object Oriented Circuit-Generators in Java.

Michael Chu, Nicholas Weaver, Kolja Sulimma, André DeHon, John Wawrzynek

Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

1997

A micropower analog circuit implementation of hidden Markov model state decoding.

John Lazzaro, John Wawrzynek, Richard P. Lippmann

IEEE J. Solid State Circuits, 1997

Garp: a MIPS processor with a reconfigurable coprocessor.

John R. Hauser, John Wawrzynek

Proceedings of the 5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 1997

Datapath-oriented FPGA mapping and placement for configurable computing.

Timothy J. Callahan, John Wawrzynek

Proceedings of the 5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 1997

1996

Spert-II: A Vector Microprocessor System.

John Wawrzynek, Krste Asanovic, Brian Kingsbury, David Johnson, James Beck, Nelson Morgan

Computer, 1996

A Micropower Analog VLSI HMM State Decoder for Wordspotting.

John Lazzaro, John Wawrzynek, Richard Lippmann

Proceedings of the Advances in Neural Information Processing Systems 9, 1996

1995

SPERT-II: A Vector Microprocessor System and its Application to Large Problems in Backpropagation Training.

John Wawrzynek, Krste Asanovic, Brian Kingsbury, James Beck, David Johnson, Nelson Morgan

Proceedings of the Advances in Neural Information Processing Systems 8, 1995

Silicon Models for Auditory Scene Analysis.

John Lazzaro, John Wawrzynek

Proceedings of the Advances in Neural Information Processing Systems 8, 1995

A multi-sender asynchronous extension to the AER protocol.

John Lazzaro, John Wawrzynek

Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI '95), 1995

1994

Systems technologies for silicon auditory models.

John Lazzaro, John Wawrzynek, Alan Kramer

IEEE Micro, 1994

1993

Using simulations of reduced precision arithmetic to design a neuro-microprocessor.

Krste Asanovic, Nelson Morgan, John Wawrzynek

J. VLSI Signal Process., 1993

The design of a neuro-microprocessor.

John Wawrzynek, Krste Asanovic, Nelson Morgan

IEEE Trans. Neural Networks, 1993

Silicon auditory processors as computer peripherals.

John Lazzaro, John Wawrzynek, Misha Mahowald, Massimo Sivilotti, Dave Gillespie

IEEE Trans. Neural Networks, 1993

Designing A Connectionist Network Supercomputer.

Krste Asanovic, James Beck, Jerry Feldman, Nelson Morgan, John Wawrzynek

Int. J. Neural Syst., 1993

1992

SPERT: a VLIW/SIMD microprocessor for artificial neural network computations.

Krste Asanovic, James Beck, Brian Kingsbury, Phil Kohn, Nelson Morgan, John Wawrzynek

Proceedings of the Application Specific Array Processors, 1992

1991

A Two-Dimensional Topological Compactor With Octagonal Geometry.

Paul de Dood, John Wawrzynek, Erwin Liu, Roberto Suaya

Proceedings of the 28th Design Automation Conference, 1991

Fine-Grain Parallelism with Minimal Hardware Support: A Compiler-Controlled Threaded Abstract Machine.

David E. Culler, Anurag Sah, Klaus E. Schauser, Thorsten von Eicken, John Wawrzynek

Proceedings of the ASPLOS-IV Proceedings, 1991

1990

VLSI Parallel Processing for Musical Sound Synthesis.

John Wawrzynek, Thorsten von Eicken

Proceedings of the 1990 International Computer Music Conference, 1990

A Multimedia Digital Signal Processing Tutoring System.

Sam Pointer, John Wawrzynek, David Wessel

Proceedings of the 1990 International Computer Music Conference, 1990

1989

The Center for New Music and Audio Technologies.

David Wessel, Richard Felciano, Adrian Freed, John Wawrzynek

Proceedings of the 1989 International Computer Music Conference, 1989

1984

A VLSI Approach to Sound Synthesis.

John Wawrzynek, Carver Mead, Tzu-Mu Lin, Hsui-Lin Liu, Lounette M. Dyer

Proceedings of the 1984 International Computer Music Conference, 1984