Alan Mishchenko

Dewmini Sudara Marakkalage

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023

Scalable Sequential Optimization Under Observability Don't Cares.

[BibT_eX]

[DOI]

CoRR, 2023

Verilog-to-PyG - A Framework for Graph Learning and Augmentation on RTL Designs.

[BibT_eX]

[DOI]

CoRR, 2023

DAG-aware Synthesis Orchestration.

[BibT_eX]

[DOI]

CoRR, 2023

Invited Paper: Verilog-to-PyG - A Framework for Graph Learning and Augmentation on RTL Designs.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Narrowing the Synthesis Gap: Academic FPGA Synthesis is Catching Up With the Industry.

[BibT_eX]

[DOI]

Benjamin Lukas Cajus Barzen

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Improving Standard-Cell Design Flow using Factored Form Optimization.

[BibT_eX]

[DOI]

Alessandro Tempia Calvino

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

A Simulation-Guided Paradigm for Logic Synthesis and Verification.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Improving LUT-based optimization for ASICs.

[BibT_eX]

[DOI]

Dewmini Sudara Marakkalage

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

Three-Input Gates for Logic Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

A Circuit-Based SAT Solver for Logic Synthesis.

[BibT_eX]

[DOI]

He-Teng Zhang

Jie-Hong R. Jiang

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Deep Integration of Circuit Simulator and SAT Solver.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

LUT-Based Optimization For ASIC Design Flow.

[BibT_eX]

[DOI]

Luca Gaetano Amarù

Vinicius N. Possani

Eleonora Testa

Felipe S. Marranghello

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

Parallel Combinational Equivalence Checking.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

SAT-Based Exact Synthesis: Encodings, Topology Families, and Parallelism.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Fast Exact NPN Classification by Co-Designing Canonical Form and Its Computation Algorithm.

[BibT_eX]

[DOI]

Xuegong Zhou

Lingli Wang

IEEE Trans. Computers, 2020

Simulation-Guided Boolean Resubstitution.

[BibT_eX]

[DOI]

CoRR, 2020

Extending Boolean Methods for Scalable Logic Synthesis.

[BibT_eX]

[DOI]

IEEE Access, 2020

SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: Design Trends, 2020

Keynote III: Boolean Logic Networks for Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020

Circuit-Based Intrinsic Methods to Detect Overfitting.

[BibT_eX]

[DOI]

Proceedings of the 37th International Conference on Machine Learning, 2020

Exact DAG-Aware Rewriting.

[BibT_eX]

[DOI]

Heinz Riener

Mathias Soeken

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set.

[BibT_eX]

[DOI]

Chang Meng

Weikang Qian

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

SAT-Sweeping Enhanced for Logic Synthesis.

[BibT_eX]

[DOI]

Luca G. Amarù

Felipe S. Marranghello

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Fast Adjustable NPN Classification Using Generalized Symmetries.

[BibT_eX]

[DOI]

Xuegong Zhou

Lingli Wang

Augusto Andre Souza Berndt

ACM Trans. Reconfigurable Technol. Syst., 2019

Effective Logic Synthesis for Threshold Logic Circuit Design.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Reduction of neural network circuits by constant and nearly constant signal propagation.

[BibT_eX]

[DOI]

Paulo Francisco Butzen

André Inácio Reis

Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019

Logic Optimization of Majority-Inverter Graphs.

[BibT_eX]

[DOI]

Proceedings of the 22nd Workshop Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2019

Scaling-up ESOP Synthesis for Quantum Compilation.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

Scalable Boolean Methods in a Modern Synthesis Flow.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Scalable Generic Logic Synthesis: One Approach to Rule Them All.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

Fast Algebraic Rewriting Based on And-Inverter Graphs.

[BibT_eX]

[DOI]

Cunxi Yu

Maciej J. Ciesielski

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

SAT-Based Fault Equivalence Checking in Functional Safety Verification.

[BibT_eX]

[DOI]

Ai Quoc Dao

Mark Po-Hung Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Pairs of majority-decomposing functions.

[BibT_eX]

[DOI]

Inf. Process. Lett., 2018

Rewriting Environment for Arithmetic Circuit Verification.

[BibT_eX]

[DOI]

Proceedings of the LPAR-22. 22nd International Conference on Logic for Programming, 2018

Unlocking fine-grain parallelism for AIG rewriting.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

Fast Adjustable NPN Classification using Generalized Symmetries.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Improving FPGA Performance with a S44 LUT Structure.

[BibT_eX]

[DOI]

Wenyi Feng

Jonathan W. Greene

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

Practical exact synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Improvements to boolean resynthesis.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Canonical computation without canonical representation.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

SAT based exact synthesis using DAG topology families.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

Efficient computation of ECO patch functions.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

SAT-based area recovery in structural technology mapping.

[BibT_eX]

[DOI]

Bruno de O. Schmitt

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Progressive Generation of Canonical Irredundant Sums of Products Using a SAT Solver.

[BibT_eX]

[DOI]

Proceedings of the Advanced Logic Synthesis, 2018

2017

Reduction of Quantum Cost by Making Temporary Changes to the Function.

[BibT_eX]

[DOI]

Nurul Ain Binti Adnan

Shigeru Yamashita

IEICE Trans. Inf. Syst., 2017

SAT solver management strategies in IC3: an experimental approach.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 2017

Enabling exact delay synthesis.

[BibT_eX]

[DOI]

Janet Olson

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Property directed reachability with word-level abstraction.

[BibT_eX]

[DOI]

Yen-Sheng Ho

Proceedings of the 2017 Formal Methods in Computer Aided Design, 2017

Busy man's synthesis: Combinational delay optimization with SAT.

[BibT_eX]

[DOI]

Mathias Soeken

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Fast-extract with cube hashing.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

m-Inductive Property of Sequential Circuits.

[BibT_eX]

[DOI]

Hamid Savoj

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT.

[BibT_eX]

[DOI]

Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2016, 2016

2QBF: Challenges and Solutions.

[BibT_eX]

[DOI]

Valeriy Balabanov

Christoph Scholl

Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2016, 2016

Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Fast hierarchical NPN classification.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Efficient uninterpreted function abstraction and refinement for word-level model checking.

[BibT_eX]

[DOI]

Proceedings of the 2016 Formal Methods in Computer-Aided Design, 2016

Clauses Versus Gates in CEGAR-Based 2QBF Solving.

[BibT_eX]

[DOI]

Valeriy Balabanov

Christoph Scholl

Proceedings of the Beyond NP, 2016

2015

Component-Based Design by Solving Language Equations.

[BibT_eX]

[DOI]

Proc. IEEE, 2015

Automated Synthesis of Protocol Converters with BALM-II.

[BibT_eX]

[DOI]

Proceedings of the Software Engineering and Formal Methods, 2015

Exploiting Circuit Duality to Speed up SAT.

[BibT_eX]

[DOI]

Luca Gaetano Amarù

Maciej J. Ciesielski

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Incremental ATPG methods for multiple faults under multiple fault models.

[BibT_eX]

[DOI]

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Threshold Logic Synthesis Based on Cut Pruning.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Improved carry chain mapping for the VTR flow.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

Technology Mapping into General Programmable Cells.

[BibT_eX]

[DOI]

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

2014

Sequential Equivalence Checking for Clock-Gated Circuits.

[BibT_eX]

[DOI]

Hamid Savoj

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Logic synthesis and verification on fixed topology.

[BibT_eX]

[DOI]

Masahiro Fujita

Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Efficient SAT-based ATPG techniques for all multiple stuck-at faults.

[BibT_eX]

[DOI]

Masahiro Fujita

Proceedings of the 2014 International Test Conference, 2014

Constrained interpolation for guided logic synthesis.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

NINJA: boolean modelling and formal verification of tiered-rate chemical reaction networks (extended abstract).

[BibT_eX]

[DOI]

Proceedings of the 5th ACM Conference on Bioinformatics, 2014

ABCD-NL: Approximating Continuous non-linear dynamical systems using purely Boolean models for analog/mixed-signal verification.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Fast Boolean matching based on NPN classification.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Trading-off Incrementality and Dynamic Restart of Multiple Solvers in IC3.

[BibT_eX]

[DOI]

Marco Palena

Gianpiero Cabodi

Proceedings of the Second International Workshop on Design and Implementation of Formal Tools and Systems, 2013

A Fast Reparameterization Procedure.

[BibT_eX]

[DOI]

Proceedings of the Second International Workshop on Design and Implementation of Formal Tools and Systems, 2013

A semi-canonical form for sequential AIGs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

GLA: gate-level abstraction revisited.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Core minimization in SAT-based abstraction.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Lazy man's logic synthesis.

[BibT_eX]

[DOI]

Wenlong Yang

Lingli Wang

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Mapping into LUT structures.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Scalable don't-care-based logic optimization and resynthesis.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2011

Delay optimization using SOP balancing.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Enhancing ABC for stabilization verification of SystemVerilog/VHDL models.

[BibT_eX]

[DOI]

Proceedings of the First International Workshop on Design and Implementation of Formal Tools and Systems, 2011

Efficient implementation of property directed reachability.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Formal Methods in Computer-Aided Design, 2011

2010

Logic synthesis and circuit customization using extensive external don't-cares.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2010

To SAT or Not to SAT: Scalable Exploration of Functional Dependency.

[BibT_eX]

[DOI]

Chih-Chun Lee

Chung-Yang Huang

IEEE Trans. Computers, 2010

Efficient FPGA Resynthesis Using Precomputed LUT Structures.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Global delay optimization using structural choices.

[BibT_eX]

[DOI]

Stephen Jang

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Combinational techniques for sequential equivalence checking.

[BibT_eX]

[DOI]

Proceedings of 10th International Conference on Formal Methods in Computer-Aided Design, 2010

A single-instance incremental SAT formulation of proof- and counterexample-based abstraction.

[BibT_eX]

[DOI]

Nina Amla

Proceedings of 10th International Conference on Formal Methods in Computer-Aided Design, 2010

Monolithically stackable hybrid FPGA.

[BibT_eX]

[DOI]

Dmitri B. Strukov

Proceedings of the Design, Automation and Test in Europe, 2010

ABC: An Academic Industrial-Strength Verification Tool.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 22nd International Conference, 2010

2009

WireMap: FPGA Technology Mapping for Improved Routability and Enhanced LUT Merging.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2009

SmartOpt: an industrial strength framework for logic synthesis.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Speculative reduction-based scalable redundancy identification.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Sequential logic synthesis using symbolic bi-decomposition.

[BibT_eX]

[DOI]

Victor N. Kravets

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Scalable and scalably-verifiable sequential synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Boolean factoring and decomposition of logic networks.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

WireMap: FPGA technology mapping for improved routability.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

Recording Synthesis History for Sequential Verification.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 2008

Invariant-Strengthened Elimination of Dependent State Elements.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 2008

Scalable min-register retiming under timing and initializability constraints.

[BibT_eX]

[DOI]

Aaron P. Hurst

Proceedings of the 45th Design Automation Conference, 2008

Merging nodes under sequential observability.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

2007

Improvements to Technology Mapping for LUT-Based FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Applying Logic Synthesis for Speeding Up SAT.

[BibT_eX]

[DOI]

Niklas Sörensson

Proceedings of the Theory and Applications of Satisfiability Testing, 2007

Combinational and sequential mapping with priority cuts.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Scalable exploration of functional dependency by interpolation and incremental SAT solving.

[BibT_eX]

[DOI]

Chih-Chun Lee

Chung-Yang Huang

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Fast Minimum-Register Retiming via Binary Maximum-Flow.

[BibT_eX]

[DOI]

Aaron P. Hurst

Proceedings of the Formal Methods in Computer-Aided Design, 7th International Conference, 2007

Automated Extraction of Inductive Invariants to Aid Model Checking.

[BibT_eX]

[DOI]

Michael L. Case

Proceedings of the Formal Methods in Computer-Aided Design, 7th International Conference, 2007

On Resolution Proofs for Combinational Equivalence.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

2006

Linear cofactor relationships in Boolean functions.

[BibT_eX]

[DOI]

Jin S. Zhang

Jerry R. Burch

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Using simulation and satisfiability to compute flexibilities in Boolean networks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

A theory of nondeterministic networks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Reducing Structural Bias in Technology Mapping.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Improvements to combinational equivalence checking.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Factor cuts.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability.

[BibT_eX]

[DOI]

Jin S. Zhang

Proceedings of the 43rd Design Automation Conference, 2006

DAG-aware AIG rewriting a fresh look at combinational logic synthesis.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

2005

Exact and Heuristic Minimization of the Average Path Length in Decision Diagrams.

[BibT_eX]

[DOI]

J. Multiple Valued Log. Soft Comput., 2005

Synthesis for regularity using decision diagrams [logic IC synthesis and layout].

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Efficient Solution of Language Equations Using Partitioned Representations.

[BibT_eX]

[DOI]

Tiziano Villa

Nina Yevtushenko

Proceedings of the 2005 Design, 2005

SAT-Based Complete Don't-Care Computation for Network Optimization.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Detecting support-reducing bound sets using two-cofactor symmetries.

[BibT_eX]

[DOI]

Jin S. Zhang

Jerry R. Burch

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

On breakable cyclic definitions.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

2003

Board-level multiterminal net assignment for the partial cross-bar architecture.

[BibT_eX]

[DOI]

Xiaoyu Song

William N. N. Hung

Andrew A. Kennings

Alan J. Coppola

IEEE Trans. Very Large Scale Integr. Syst., 2003

Fast computation of symmetries in Boolean functions.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

A Theory of Non-Deterministic Networks.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Reducing Multi-Valued Algebraic Operations to Binary.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

A new enhanced constructive decomposition and mapping algorithm.

[BibT_eX]

[DOI]

Xinning Wang

Timothy Kam

Proceedings of the 40th Design Automation Conference, 2003

Large-scale SOP minimization using decomposition and functional properties.

[BibT_eX]

[DOI]

Tsutomu Sasao

Proceedings of the 40th Design Automation Conference, 2003

2002

Generalized Inclusive Forms - New Canonical Reed-Muller Forms Including Minimum ESOPs.

[BibT_eX]

[DOI]

VLSI Design, 2002

Encoding of Boolean Functions and its Application to LUT Cascade Synthesis.

[BibT_eX]

Tsutomu Sasao

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Logic Synthesis of Reversible Wave Cascades.

[BibT_eX]

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

A Boolean Paradigm in Multi-Valued Logic Synthesis.

[BibT_eX]

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Optimization of Multi-Valued Multi-Level Networks.

[BibT_eX]

[DOI]

M. Gao

Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

Topologically constrained logic synthesis.

[BibT_eX]

[DOI]

Subarnarekha Sinha

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Simplification of non-deterministic multi-valued networks.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Board-level multiterminal net assignment.

[BibT_eX]

[DOI]

Xiaoyu Song

William N. N. Hung

Alan J. Coppola

Andrew A. Kennings

Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

2001

Regular Realization of Symmetric Functions Using Reversible Logic.

[BibT_eX]

[DOI]

Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

An Algorithm for Bi-Decomposition of Logic Functions.

[BibT_eX]

[DOI]

Bernd Steinbach

Proceedings of the 38th Design Automation Conference, 2001

1999

Evolvable Hardware or Learning Hardware? Induction of State Machines from Temporal Logic Constraints.

[BibT_eX]

[DOI]