Diana Göhringer

Orcid: 0000-0003-2571-8441

Affiliations:
  • TU Dresden, Germany
  • Ruhr University Bochum, Germany (former)


According to our database1, Diana Göhringer authored at least 200 papers between 2006 and 2024.

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Bibliography

2024
Introduction to the FPL 2021 Special Section.
ACM Trans. Reconfigurable Technol. Syst., March, 2024

Exploration of Power-Savings on Multi-Core Architectures With Offloaded Real-Time Operating System.
IEEE Access, 2024

A Flexible Mixed-Mesh FPGA Cluster Architecture for High Speed Computing.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2024

Trusted Computing Architectures for IoT Devices.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2024

2023
Guest Editors Introduction: Special Issue on Network-on-Chip Architectures of the Future (NoCArc).
ACM J. Emerg. Technol. Comput. Syst., July, 2023

Near-memory Computing on FPGAs with 3D-stacked Memories: Applications, Architectures, and Optimizations.
ACM Trans. Reconfigurable Technol. Syst., March, 2023

NDP-RANK: Prediction and ranking of NDP systems performance using machine learning.
Microprocess. Microsystems, February, 2023

A Survey on Adaptive Computing in Robotics: Modelling, Methods and Applications.
IEEE Access, 2023

Unlocking the Potential of RISC-V Heterogeneous MPSoC: A PANACA-Based Approach to Simulation and Modeling.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023

Enhancing Robustness and Reliability of Networks-on-Chip with Network Coding.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023

X-MAPE: Extending 6G-Connected Self-Adaptive Systems with Reflexive Actions.
Proceedings of the IEEE Conference on Network Function Virtualization and Software Defined Networks, 2023

A Near-Memory Dynamically Programmable Many-Core Overlay.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

Performance Estimation and Prototyping of Reconfigurable Near-Memory Computing Systems.
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

Compiler-Assisted Kernel Selection for FPGA-based Near-Memory Computing Platforms.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

Virtualization of Hardware Accelerators in a Network-on-Chip.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

Auto-DOK: Compiler-Assisted Automatic Detection of Offload Kernels for FPGA-HBM Architectures.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

RTASS: a RunTime Adaptable and Scalable System for Network-on-Chip-Based Architectures.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

Investigating the Impact of Non-Volatile Memories on Energy-Efficiency of Coarse-Grained Reconfigurable Architectures.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

EuFRATE: European FPGA Radiation-hardened Architecture for Telecommunications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Welcome Message from the Chairs.
Proceedings of the IEEE International Conference on Omni-layer Intelligent Systems, 2023

An Efficient Accelerator for Nonlinear Model Predictive Control.
Proceedings of the 34th IEEE International Conference on Application-specific Systems, 2023

ArcvaVX: OpenVX Framework for Adaptive Reconfigurable Computer Vision Architectures.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2023

Simulation and Modelling for Network-on-Chip Based MPSoC.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2023

2022
RTOS-supported low power scheduling of periodic hardware tasks in flash-based FPGAs.
Microprocess. Microsystems, July, 2022

Object Recognition in High-Resolution Indoor THz SAR Mapped Environment.
Sensors, 2022

A cross-platform OpenVX library for FPGA accelerators.
J. Syst. Archit., 2022

AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors.
IEEE Access, 2022

PANACA: An Open-Source Configurable Network-on-Chip Simulation Platform.
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022

GraphCL: A Framework for Execution of Data-Flow Graphs on Multi-Device Platforms.
Proceedings of the 30th Euromicro International Conference on Parallel, 2022

DECISION: Distributing OpenVX Applications on CPUs, GPUs and FPGAs using OpenCL.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022

Modeling FPGA-based Architectures for Robotics.
Proceedings of the International Conference on Field-Programmable Technology, 2022

An Agile Tile-based Platform for Adaptive Heterogeneous Many-Core Systems.
Proceedings of the International Conference on Field-Programmable Technology, 2022

Energy Efficient Design of Coarse-Grained Reconfigurable Architectures: Insights, Trends and Challenges.
Proceedings of the International Conference on Field-Programmable Technology, 2022

Application Specific Instruction-Set Processors for Machine Learning Applications.
Proceedings of the International Conference on Field-Programmable Technology, 2022

Virtualization of Embedded Reconfigurable Systems.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

Virtualization of Reconfigurable Mixed-Criticality Systems.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

Model-based Generation of Hardware/Software Architectures for Robotics Systems.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

A Hybrid Memory/Accelerator Tile Architecture for FPGA-based RISC-V Manycore Systems.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

A Framework for Intrinsic Evolvable Systems.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

Scheduling of Hardware Tasks in Reconfigurable Mixed-Criticality Systems.
Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022

MaNaBIT: A Versatile Tool for Manipulating and Analyzing FPGA Bitstreams.
Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022


High-Performance AKAZE Implementation Including Parametrizable and Generic HLS Modules.
Proceedings of the 33rd IEEE International Conference on Application-specific Systems, 2022

Secure Communication Protocol for Network-on-Chip with Authenticated Encryption and Recovery Mechanism.
Proceedings of the 33rd IEEE International Conference on Application-specific Systems, 2022

2021
A Parametrizable High-Level Synthesis Library for Accelerating Neural Networks on FPGAs.
J. Signal Process. Syst., 2021

Model-Based Approach for Automatic Generation of Hardware Architectures for Robotics.
IEEE Access, 2021

Performance analysis of application-specific instruction-set routers in networks-on-chip.
Proceedings of the NoCArc '21: Proceedings of the 14th International Workshop on Network on Chip Architectures, Virtual Event, Greece, October 18, 2021

RV-CAP: Enabling Dynamic Partial Reconfiguration for FPGA-Based RISC-V System-on-Chip.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2021

CoopCL: A Framework for Cooperative Execution of Data-parallel Kernels on Multi-device Platforms.
Proceedings of the HEART '21: 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2021

AMAH-Flex: A Modular and Highly Flexible Tool for Generating Relocatable Systems on FPGAs.
Proceedings of the International Conference on Field-Programmable Technology, 2021

A Survey on Hypervisor-based Virtualization of Embedded Reconfigurable Systems.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

Wormhole Computing in Networks-on-Chip.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

Reconfigurable Computing Systems as Component-oriented Designs for Robotics.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

Design For Agility: A Modular Reconfigurable Platform for Heterogeneous Many-Core Architectures.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

AITIA: Embedded AI Techniques for Industrial Applications.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

Power-Aware Real-Time Operating Systems on Reconfigurable Architectures.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

Power-Aware Computing Systems on FPGAs: A Survey.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

Optimized Deep Learning Object Recognition for Drones using Embedded GPU.
Proceedings of the 26th IEEE International Conference on Emerging Technologies and Factory Automation, 2021

Near-Data-Processing Architectures Performance Estimation and Ranking using Machine Learning Predictors.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

Vector Processing Unit: A RISC-V based SIMD Co-processor for Embedded Processing.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

2020
SDMPSoC: Software-Defined MPSoC for FPGAs.
J. Signal Process. Syst., 2020

Guest Editorial Note: Special Issue on Applied Reconfigurable Computing.
J. Signal Process. Syst., 2020

HPPT-NoC: A Dark-Silicon Inspired Hierarchical TDM NoC with Efficient Power-Performance Trading.
IEEE Trans. Parallel Distributed Syst., 2020

Optimizing the Operational Time of Ambient Assisting Living Robots.
IEEE Consumer Electron. Mag., 2020

Toward an ICT-Based Service Oriented Health Care Paradigm.
IEEE Consumer Electron. Mag., 2020

Towards a Modular RISC-V Based Many-Core Architecture for FPGA Accelerators.
IEEE Access, 2020

Indoor THz SAR Trajectory Deviations Effects and Compensation With Passive Sub-mm Localization System.
IEEE Access, 2020

Experimental Analysis of High Resolution Indoor THz SAR Imaging.
Proceedings of the 24th International ITG Workshop on Smart Antennas, 2020

CoopCL: Cooperative Execution of OpenCL Programs on Heterogeneous CPU-GPU Platforms.
Proceedings of the 28th Euromicro International Conference on Parallel, 2020

Low Power Scheduling of Periodic Hardware Tasks in Flash-Based FPGAs.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2020, Oslo, 2020

Energy Efficient Synchronous - Asynchronous Circuit-Switched NoC.
Proceedings of the 9th International Conference on Modern Circuits and Systems Technologies, 2020

AITIA: Embedded AI Techniques for Embedded Industrial Applications.
Proceedings of the 2020 International Conference on Omni-layer Intelligent Systems, 2020

Cycle-Accurate Debugging of Embedded Designs Using Recurrent Neural Networks.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020

RISC-V Based MPSoC Design Exploration for FPGAs: Area, Power and Performance.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020

SysIDLib: A High-Level Synthesis FPGA Library for Online System Identification.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020

Resource Efficient Dynamic Voltage and Frequency Scaling on Xilinx FPGAs.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020

2019
Whisper: Fast Flooding for Low-Power Wireless Networks.
ACM Trans. Sens. Networks, 2019

Intrusive FPGA-in-the-loop debugging using a rule-based inference system.
Microprocess. Microsystems, 2019

A framework for accelerating local feature extraction with OpenCL on multi-core CPUs and co-processors.
J. Real Time Image Process., 2019

Scalable clustering and mapping algorithm for application distribution on heterogeneous and irregular FPGA clusters.
J. Parallel Distributed Comput., 2019

FPGA-ROS: Methodology to Augment the Robot Operating System with FPGA Designs.
Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019

Cycle-Accurate Debugging of Multi-clock Reconfigurable Systems.
Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019

Modular Memory System for RISC-V Based MPSoCs on Xilinx FPGAs.
Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

Dark-Silicon Inspired Energy Efficient Hierarchical TDM NoC.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Inspection of Partial Bitstreams for FPGAs Using Artificial Neural Networks.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019

Hardware/Software-Codesign for Hand Gestures Recognition using a Convolutional Neural Network.
Proceedings of the INTESA 2019 Proceedings, 2019

System Identification using LMS, RLS, EKF and Neural Network.
Proceedings of the IEEE International Conference of Vehicular Electronics and Safety, 2019

IP Core Identification in FPGA Configuration Files using Machine Learning Techniques.
Proceedings of the 9th IEEE International Conference on Consumer Electronics, 2019

Efficient Pattern Recognition Algorithm Including a Fast Retina Keypoint FPGA Implementation.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

HiFlipVX: An Open Source High-Level Synthesis FPGA Library for Image Processing.
Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019

2018
Application Deployment Strategies for Spatial Isolation on Many-Core Accelerators.
ACM Trans. Embed. Comput. Syst., 2018

Sensor data fusion in the context of electric vehicles charging stations using a Network-on-Chip.
Microprocess. Microsystems, 2018

ASIR: Application-Specific Instruction-Set Router for NoC-Based MPSoCs.
Comput., 2018

Full-HD Accelerated and Embedded Feature Detection Video System with 63fps using ORB for FREAK.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

Dynamic tunable and reconfigurable hardware controller with EKF-based state reconstruction through FPGA-in the loop.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

Analysis of Synchronous-Asynchronous NoC for the Dark Silicon Era.
Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018

Introduction to RAW 2018.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

Automatic Mapping for OpenCL-Programs on CPU/GPU Heterogeneous Platforms.
Proceedings of the Computational Science - ICCS 2018, 2018

Automatic OpenCL Code Generation from LLVM-IR using Polyhedral Optimization.
Proceedings of the 9th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and 7th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2018

Cycle-Accurate and Cycle-Reproducible Debugging of Embedded Designs Using Artificial Intelligence.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Low Power Image Processing Applications on FPGAs Using Dynamic Voltage Scaling and Partial Reconfiguration.
Proceedings of the 2018 Conference on Design and Architectures for Signal and Image Processing, 2018

Supporting Utilities for Heterogeneous Embedded Image Processing Platforms (STHEM): An Overview.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

High-Level Synthesis of Software-Defined MPSoCs.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

An Intrusive Dynamic Reconfigurable Cycle-Accurate Debugging System for Embedded Processors.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO Experience.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017
Survey on Real-Time Networks-on-Chip.
IEEE Trans. Parallel Distributed Syst., 2017

Special issue on design of algorithms and architectures for signal and image processing.
J. Syst. Archit., 2017

HW/SW Co-Design of the HOG algorithm on a Xilinx Zynq SoC.
J. Parallel Distributed Comput., 2017

Tackling The New Health-Care Paradigm Through Service Robotics: Unobtrusive, efficient, reliable, and modular solutions for assisted-living environments.
IEEE Consumer Electron. Mag., 2017

An event-based Network-on-Chip debugging system for FPGA-based MPSoCs.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Application-specific processing using high-level synthesis for networks-on-chip.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

A call-up for circuit-switched NoCs in the Dark-Silicon Era.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017

Data Stream Processing in Networks-on-Chip.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Profile-Driven Power Optimizations for AAL Robots: Maximizing Robots Idle Time by Offloading Monitoring Workload to Dedicated Hardware Components.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

HW/SW Co-design of an IEEE 802.11a/g Receiver on Xilinx Zynq SoC using High-Level Synthesis.
Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

Access Network Generation for Efficient Debugging of FPGAs.
Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

Accelerated Embedded AKAZE Feature Detection Algorithm on FPGA.
Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

Exploration of OpenCL for FPGAs using SDAccel and comparison to GPUs and multicore CPUs.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Robust lane recognition for autonomous driving.
Proceedings of the 2017 Conference on Design and Architectures for Signal and Image Processing, 2017

FPGA Debugging with MATLAB Using a Rule-Based Inference System.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017

2016
Simulating Reconfigurable Multiprocessor Systems-on-Chip with MPSoCSim.
ACM Trans. Embed. Comput. Syst., 2016

Enabling indoor object localization through Bluetooth beacons on the RADIO robot platform.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

MPSoCSim extension: An OVP simulator for the evaluation of cluster-based multi and many-core architectures.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

TULIPP: Towards ubiquitous low-power image processing platforms.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Dynamic spatially isolated secure zones for NoC-based many-core accelerators.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

RePaBit: Automated generation of relocatable partial bitstreams for Xilinx Zynq FPGAs.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

FPGA debugging by a device start and stop approach.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Enabling dynamic and partial reconfiguration in Xilinx SDSoC.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Sensor data fusion with MPSoCSim in the context of electric vehicle charging stations.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

RAW Introduction and Committees.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

LinROS: A Linux-Based Runtime System for Reconfigurable MPSoCs.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

Clustering and Mapping Algorithm for Application Distribution on a Scalable FPGA Cluster.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

ARTNoCs: An Evaluation Framework for Hardware Architectures of Real-Time NoCs.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

Development of advanced driver assistance systems using LabVIEW and a car simulator.
Proceedings of the 2016 Workshop on Embedded and Cyber-Physical Systems Education, 2016

Computation and communication challenges to deploy robots in assisted living environments.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Session 3: Method and tools for system design.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

2015
Guest Editorial ARC 2014.
ACM Trans. Reconfigurable Technol. Syst., 2015

MPSoCSim: An extended OVP simulator for modeling and evaluation of Network-on-Chip based heterogeneous MPSoCs.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

ViPES 2015 - Preface.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Real-time pedestrian detection on a xilinx zynq using the HOG algorithm.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

RAW Introduction and Committees.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

Online bicast allocation algorithm for contention-free-routing NoCs.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

A Holistic Approach for Advancing Robots in Ambient Assisted Living Environments.
Proceedings of the 13th IEEE International Conference on Embedded and Ubiquitous Computing, 2015

Robot navigation based on an efficient combination of an extended A∗ algorithm, bird's eye view and image stitching.
Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015

A Flexible Software Framework for Dynamic Task Allocation on MPSoCs Evaluated in an Automotive Context.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

DynamIA: Dynamic Hardware Reconfiguration in Industrial Applications.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

Survey on Real-Time Network-on-Chip Architectures.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO Perspective.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014
Introduction to the Special Issue on Virtual Prototyping of Parallel and Embedded Systems (ViPES).
ACM Trans. Embed. Comput. Syst., 2014

Reconfigurable Multiprocessor Systems: Handling Hydras Heads - A Survey.
SIGARCH Comput. Archit. News, 2014

Special Issue on Networks-on-Chip and Memories for Multicore Architectures.
Microprocess. Microsystems, 2014

Using JSON to manage communication between services in the Internet of Things.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

RAR-NoC: A reconfigurable and adaptive routable Network-on-Chip for FPGA-based multiprocessor systems.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Parallel and distributed simulation of networked multi-core systems.
Proceedings of the 2014 International Symposium on System-on-Chip, 2014

Future Trends on Adaptive Processing Systems.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

Development of driver assistance systems using virtual hardware-in-the-loop.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

An Interactive Tool based on Polly for Detection and Parallelization of Loops.
Proceedings of the 5th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 3rd Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2014

Accelerating local feature extraction using OpenCL on heterogeneous platforms.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

2013
Introduction to the special section on 19th reconfigurable architectures workshop (RAW 2012).
ACM Trans. Reconfigurable Technol. Syst., 2013

Reliable and adaptive network-on-chip architectures for cyber physical systems.
ACM Trans. Embed. Comput. Syst., 2013

Rapid prototyping of a portable HW/SW co-design on the virtual zynq platform using SystemC.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

Dynamic and partial reconfiguration of Zynq 7000 under Linux.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Evaluation of driver assistance systems with a car simulator using a virtual and a real FPGA platform.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

2012
Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration.
Int. J. Reconfigurable Comput., 2012

Adaptive processor architecture - invited paper.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012


Special session on "programming paradigms for reconfigurable multi-core embedded systems".
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

A flexible approach for compiling scilab to reconfigurable multi-core embedded systems.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Invited paper: On-chip monitoring for adaptive heterogeneous multicore systems.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

From Scilab to High Performance Embedded Multicore Systems: The ALMA Approach.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Virtualized on-chip distributed computing for heterogeneous reconfigurable multi-core systems.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Virtualization of heterogeneous and adaptive multi-core/multi-board systems.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

2011
Flexible Design and Dynamic Utilization of Adaptive Scalable Multi-Core Systems.
PhD thesis, 2011

Exploration of the Power-Performance Tradeoff through Parameterization of FPGA-Based Multiprocessor Systems.
Int. J. Reconfigurable Comput., 2011

Operating System for Runtime Reconfigurable Multiprocessor Systems.
Int. J. Reconfigurable Comput., 2011

Heterogeneous and runtime parameterizable Star-Wheels Network-on-Chip.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Dynamic Processor Reconfiguration.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Adaptive Multi-client Network-on-Chip Memory.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Power and performance optimization through MPI supported dynamic voltage and frequency scaling.
Proceedings of the 3rd Many-core Applications Research Community (MARC) Symposium. Proceedings of the 3rd MARC Symposium, 2011

RAMPSoCVM: Runtime Support and Hardware Virtualization for a Runtime Adaptive MPSoC.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Adaptive Multiprocessor System-on-Chip Architecture: New Degrees of Freedom in System Design and Runtime Support.
Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011

2010
Message Passing Interface support for the runtime adaptive multi-processor system-on-chip RAMPSoC.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Impact of Task Distribution, Processor Configurations and Dynamic Clock Frequency Scaling on the Power Consumption of FPGA-based Multiprocessors.
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010

New Dimensions in Design Space and Runtime Adaptivity for Multiprocessor Systems Through Dynamic and Partial Reconfiguration: The RAMPSoC Approach.
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010

FPGA-Based Runtime Adaptive Multiprocessor Approach for Embedded High Performance Computing Applications.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Fast dynamic and partial reconfiguration data path with low hardware overhead on Xilinx FPGAs.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

CAP-OS: Operating system for runtime scheduling, task mapping and resource management on reconfigurable multiprocessor architectures.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

High performance reconfigurable multi-processor-based computing on FPGAs.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

A semi-automatic toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning (abstract only).
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

A Design Methodology for Application Partitioning and Architecture Development of Reconfigurable Multiprocessor Systems-on-Chip.
Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

Performance, accuracy, power consumption and resource utilization analysis for hardware / software realized Artificial Neural Networks.
Proceedings of the Fifth International Conference on Bio-Inspired Computing: Theories and Applications, 2010

2009
Adaptive real-time image processing exploiting two dimensional reconfigurable architecture.
J. Real Time Image Process., 2009

A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip.
Int. J. Reconfigurable Comput., 2009

Star-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a packet-switching communication protocol.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008
Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Runtime adaptive multi-processor system-on-chip: RAMPSoC.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

New dimensions for multiprocessor architectures: Ondemand heterogeneity, infrastructure and performance through reconfigurability - the RAMPSoC approach.
Proceedings of the FPL 2008, 2008

2007
The Erlangen Slot Machine - A Platform for Interdisciplinary Research in Dynamically Reconfigurable Computing (ESM - Eine Hardware-Plattform für interdisziplinäre Forschung im Bereich des dynamischen rekonfigurierbaren Rechnens).
it Inf. Technol., 2007

2006
Bridging the Gap between Relocatability and Available Technology: The Erlangen Slot Machine.
Proceedings of the Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006, 2006


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