Jorgen Christiansen

According to our database, Jorgen Christiansen authored at least 7 papers between 1996 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2016

A single-event upset robust, 2.2 GHz to 3.2 GHz, 345 fs jitter PLL with triple-modular redundant phase detector in 65 nm CMOS.

Jeffrey Prinzie, Michiel Steyaert, Paul Leroux, Jorgen Christiansen, Paulo Moreira

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015

Reusable SystemVerilog-UVM design framework with constrained stimuli modeling for High Energy Physics applications.

Sara Marconi, Elia Conti, Jorgen Christiansen, Pisana Placidi

Proceedings of the IEEE International Symposium on Systems Engineering, 2015

A SystemVerilog-UVM Methodology for the Design, Simulation and Verification of Complex Readout Chips in High Energy Physics Applications.

Sara Marconi, Elia Conti, Pisana Placidi, Andrea Scorzoni, Jorgen Christiansen, Tomasz Hemperek

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2015

2013

A fine time-resolution (<3 ps-rms) time-to-digital converter for highly integrated designs.

Lukas Perktold, Jorgen Christiansen

Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2013

1999

A high-resolution time interpolator based on a delay locked loop and an RC delay line.

Manuel Mota, Jorgen Christiansen

IEEE J. Solid State Circuits, 1999

1998

A four channel, self-calibrating, high resolution, time to digital converter.

Manuel Mota, Jorgen Christiansen

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1996

An integrated high resolution CMOS timing generator based on an array of delay locked loops.

Jorgen Christiansen

IEEE J. Solid State Circuits, 1996