Paul Leroux

Orcid: 0000-0002-1790-2428

Affiliations:
  • Catholic University of Leuven, Belgium


According to our database1, Paul Leroux authored at least 29 papers between 2002 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
A 10 MS/s 12-bit Cryogenic SAR ADC in 22nm FD SOI for Quantum Computing.
Proceedings of the 22nd IEEE Interregional NEWCAS Conference, 2024

An 80MS/s 70.79dB-SNDR 60.7fJ/Conv-Step Radiation-Tolerant Semi-Time-interleaved Pipelined-SAR ADC.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023
A CDAC Mismatch Calibration Technique for SAR-assisted Pipeline ADCs.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

2021
Tradeoffs in Time-to-Digital Converter Architectures for Harsh Radiation Environments.
IEEE Trans. Instrum. Meas., 2021

Pseudo-Differential Time-Domain Integrator Using Charge-Based Time-Domain Circuits.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

A 0.18 pJ/Step Time-Domain 1st Order ΔΣ Capacitance-to-Digital Converter in 65-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit With High Speed Feed Forward Correction in 65 nm CMOS.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

Effect of Temperature on Single Event Latchup Sensitivity.
Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020

2019
Practical Driving Electronics for an AOTF-Based NO<sub>2</sub> Camera.
IEEE Trans. Instrum. Meas., 2019

A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit with High Speed Feed Forward Correction in 65 nm CMOS.
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

2018
Analysis of the charge sharing effect in the SET sensitivity of bulk 45 nm standard cell layouts under heavy ions.
Microelectron. Reliab., 2018

2017
Highly Tunable Triangular Wave UWB Baseband Pulse Generator With Amplitude Stabilization in 40-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

2016
A Self-Calibrated Bang-Bang Phase Detector for Low-Offset Time Signal Processing.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A single-event upset robust, 2.2 GHz to 3.2 GHz, 345 fs jitter PLL with triple-modular redundant phase detector in 65 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
Embedded DSP-Based Telehealth Radar System for Remote In-Door Fall Detection.
IEEE J. Biomed. Health Informatics, 2015

Direct RF Subsampling Receivers Enabling Impulse-Based UWB Signals for Breast Cancer Detection.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

RF-driving of acoustic-optical tunable filters; design, realization and qualification of analog and digital modules for ESA.
Microelectron. Reliab., 2015

A 280 ps - 7.5 ns UWB Pulse Generator with Amplitude Compensation in 40 nm CMOS.
Proceedings of the IEEE International Conference on Ubiquitous Wireless Broadband, 2015

Experimental validation of a compact model for EM reflection and transmission in multi-layered structures.
Proceedings of the 2015 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings, 2015

2014
Healthcare System for Non-invasive Fall Detection in Indoor Environment.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2014

2013
A 63, 000 Q-factor relaxation oscillator with switched-capacitor integrated error feedback.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
1-1-1 MASH Δ Σ Time-to-Digital Converters With 6 ps Resolution and Third-Order Noise-Shaping.
IEEE J. Solid State Circuits, 2012

2011
A 1.7mW 11b 1-1-1 MASH ΔΣ time-to-digital converter.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 0.7mW 13b temperature-stable MASH ΔΣ TDC with delay-line assisted calibration.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2005
ESD-RF co-design methodology for the state of the art RF-CMOS blocks.
Microelectron. Reliab., 2005

2004
A 5 GHz CMOS low-noise amplifier with inductive ESD protection exceeding 3 kV HBM.
Proceedings of the 33rd European Solid-State Circuits Conference, 2004

Two high-speed optical front-ends with integrated photodiodes in standard 0.18 μm CMOS.
Proceedings of the 33rd European Solid-State Circuits Conference, 2004

2002
A 0.8-dB NF ESD-Protected 9-mW CMOS LNA operating at 1.23 GHz [for GPS receiver].
IEEE J. Solid State Circuits, 2002

Optimization of a fully integrated low power CMOS GPS receiver.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002


  Loading...