Julien Schmaltz
According to our database1,
Julien Schmaltz
authored at least 53 papers
between 2003 and 2021.
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Bibliography
2021
Springer, ISBN: 978-3-030-68552-2, 2021
2020
Proceedings of the 2020 Formal Methods in Computer Aided Design, 2020
2018
Automatic generation of hardware checkers from formal micro-architectural specifications.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
2016
Proceedings of the International Workshop on MILS: Architecture and Assurance for Secure Systems, 2016
2015
Proceedings of the NASA Formal Methods - 7th International Symposium, 2015
Process algebra semantics & reachability analysis for micro-architectural models of communication fabrics.
Proceedings of the 13. ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2015
Proceedings of the International Workshop on MILS: Architecture and Assurance for Secure Systems, 2015
Automatic extraction of micro-architectural models of communication fabrics from register transfer level designs.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
IEEE Trans. Parallel Distributed Syst., 2014
Inference of channel types in micro-architectural models of on-chip communication networks.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
Proceedings of the Computer Safety, Reliability, and Security, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Proceedings of the Proceedings International Workshop on the ACL2 Theorem Prover and its Applications, 2013
Proceedings of the Proceedings International Workshop on the ACL2 Theorem Prover and its Applications, 2013
Proceedings of the Proceedings International Workshop on the ACL2 Theorem Prover and its Applications, 2013
Generation of inductive invariants from register transfer level designs of communication fabrics.
Proceedings of the 11th ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2013
Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013
2012
ACM Trans. Design Autom. Electr. Syst., 2012
Easy Formal Specification and Validation of Unbounded Networks-on-Chips Architectures.
ACM Trans. Design Autom. Electr. Syst., 2012
Theor. Comput. Sci., 2012
Proof Pearl: A Formal Proof of Dally and Seitz' Necessary and Sufficient Condition for Deadlock-Free Routing in Interconnection Networks.
J. Autom. Reason., 2012
A formally verified deadlock-free routing function in a fault-tolerant NoC architecture.
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012
Automatic generation of deadlock detection algorithms for a family of microarchitecture description languages of communication fabrics.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012
2011
On Necessary and Sufficient Conditions for Deadlock-Free Routing in Wormhole Networks.
IEEE Trans. Parallel Distributed Syst., 2011
A Comment on "A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks".
IEEE Trans. Parallel Distributed Syst., 2011
Proceedings of the Proceedings 10th International Workshop on the ACL2 Theorem Prover and its Applications, 2011
Proceedings of the 19th International Euromicro Conference on Parallel, 2011
Automatic verification for deadlock in networks-on-chips with adaptive routing and wormhole switching.
Proceedings of the NOCS 2011, 2011
An Experience Report on an Industrial Case-Study about Timed Model-Based Testing with UPPAAL-TRON.
Proceedings of the Fourth IEEE International Conference on Software Testing, 2011
Proceedings of the International Conference on Formal Methods in Computer-Aided Design, 2011
2010
A Formal Proof of a Necessary and Sufficient Condition for Deadlock-Free Adaptive Networks.
Proceedings of the Interactive Theorem Proving, First International Conference, 2010
Proceedings of the Leveraging Applications of Formal Methods, Verification, and Validation, 2010
Proceedings of the Formal Modeling and Analysis of Timed Systems, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
EURASIP J. Embed. Syst., 2009
Proceedings of the Formal Methods for Industrial Critical Systems, 2009
Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, 2009
2008
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008
Proceedings of the Formal Modeling and Analysis of Timed Systems, 2008
2007
A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study.
Proceedings of the First International Symposium on Networks-on-Chips, 2007
A Formal Model of Clock Domain Crossing and Automated Verification of Time-Triggered Hardware.
Proceedings of the Formal Methods in Computer-Aided Design, 7th International Conference, 2007
2006
Proceedings of the Formal Methods in Computer-Aided Design, 6th International Conference, 2006
Proceedings of the Workshop "Trustworthy Software" 2006, 2006
Proceedings of the Sixth International Workshop on the ACL2 Theorem Prover and its Applications, 2006
2005
Proceedings of the Theorem Proving in Higher Order Logics, 18th International Conference, 2005
2004
TheoSim: combining symbolic simulation and theorem proving for hardware verification.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004
Proceedings of the Formal Methods in Computer-Aided Design, 5th International Conference, 2004
2003
Proceedings of the Correct Hardware Design and Verification Methods, 2003