Amr Helmy

According to our database1, Amr Helmy authored at least 15 papers between 2007 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2018
A Low Power CORDIC-Based Hardware Implementation of Izhikevich Neuron Model.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

HEVC Implementation for IoT Applications.
Proceedings of the 30th International Conference on Microelectronics, 2018

ASIC Implementation of Energy-Optimized Successive Cancellation Polar Decoders for Internet of Things.
Proceedings of the 30th International Conference on Microelectronics, 2018

2017
A Novel CMOS-Based Fully Differential Operational Floating Conveyor.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

An improved design for high speed analog applications of the fully differential operational floating conveyor.
Proceedings of the 29th International Conference on Microelectronics, 2017

2015
VHDL implementation of a power management algorithm for PV-battery system.
Proceedings of the 5th International Conference on Energy Aware Computing Systems & Applications, 2015

Dual output power management unit for a PV-battery hybrid energy system.
Proceedings of the 5th International Conference on Energy Aware Computing Systems & Applications, 2015

2013
VHDL implementation of Maximum Power Point Tracking algorithms.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

TPQA: Three point quadrature approximation MPPT algorithm.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

2012
Synthesizable delay line architectures for digitally controlled voltage regulators.
Proceedings of the IEEE 25th International SOC Conference, 2012

Redundancy and ECC mechanisms to improve energy efficiency of on-die interconnects.
Proceedings of the International Conference on Energy Aware Computing, 2012

2010
Theorem proving techniques for the formal verification of NoC communications with non-minimal adaptive routing.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009
A Formal Approach to the Verification of Networks on Chip.
EURASIP J. Embed. Syst., 2009

2008
Executable formal specification and validation of NoC communication infrastructures.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

2007
A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study.
Proceedings of the First International Symposium on Networks-on-Chips, 2007


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