Jun-Hong Chen

According to our database1, Jun-Hong Chen authored at least 19 papers between 2004 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Animated Character Style Investigation with Decision Tree Classification.
Symmetry, 2020

2019
A Study of Facial Features of American and Japanese Cartoon Characters.
Symmetry, 2019

2017
SheddomeDB: the ectodomain shedding database for membrane-bound shed markers.
BMC Bioinform., 2017

Freeway Travel Time Prediction by Using the GA-Based Hammerstein Recurrent Neural Network.
Proceedings of the Genetic and Evolutionary Computing, 2017

2010
A High-Performance Unified-Field Reconfigurable Cryptographic Processor.
IEEE Trans. Very Large Scale Integr. Syst., 2010

2009
A New Algorithm for High-Speed Modular Multiplication Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

An Efficient Multiplier/Divider Design for Elliptic Curve Cryptosystem over GF(2m).
J. Inf. Sci. Eng., 2009

2008
A New Modular Exponentiation Architecture for Efficient Design of RSA Cryptosystem.
IEEE Trans. Very Large Scale Integr. Syst., 2008

A new look-up table-based multiplier/squarer design for cryptosystems over GF(2<sup>m</sup>).
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

High-speed modular multiplication design for public-key cryptosystems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Exploration of Low-Cost Configurable S-Box Designs for AES Applications.
Proceedings of the International Conference on Embedded Software and Systems, 2008

2007
A New Montgomery Modular Multiplication Algorithm and its VLSI Design for RSA Cryptosystem.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
High-Speed Design of Montgomery Inverse Algorithm over GF(2<sup><i>m</i></sup>).
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Design and implementation of efficient Reed-Solomon decoders for multi-mode applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

High-speed CRC design for 10 Gbps applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Asynchronous Design of Modular Multiplication Using Adaptive Radix Computation.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
VLSI architectural design tradeoffs for sliding-window log-MAP decoders.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Concurrent algorithm for high-speed point multiplication in elliptic curve cryptography.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
VLSI architecture exploration for sliding-window Log-MAP decoders.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004


  Loading...