Ming-Der Shieh

According to our database1, Ming-Der Shieh authored at least 100 papers between 1993 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
uFETCH: A Unified Searchable Encryption Scheme and Its Saas-Native to Make DBMS Privacy-Preserving.
IEEE Access, 2020

2019
Efficient Comparison and Swap on Fully Homomorphic Encrypted Data.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Architecture-aware Memory Access Scheduling for High-throughput Cascaded Classifiers.
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

2018
Low-Complexity VLSI Design of Large Integer Multipliers for Fully Homomorphic Encryption.
IEEE Trans. Very Large Scale Integr. Syst., 2018

High-performance NTT architecture for large integer multiplication.
Proceedings of the 2018 International Symposium on VLSI Design, 2018

A Security Proxy to Cloud Storage Backends Based on an Efficient Wildcard Searchable Encryption.
Proceedings of the 8th IEEE International Symposium on Cloud and Service Computing, 2018

Minimizing ESOP Expressions for Fully Homomorphic Encryption.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Fast Keyframe Selection and Switching for ICP-based Camera Pose Estimation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Content-aware line-based power modeling methodology for image signal processor.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

2016
Motion-Aware Iterative Closest Point Estimation for Fast Visual Odometry.
Proceedings of the 2016 IEEE International Symposium on Mixed and Augmented Reality, 2016

Effective Registration for Multiple Users AR System.
Proceedings of the 2016 IEEE International Symposium on Mixed and Augmented Reality, 2016

Fast model searching and combining for example learning-based super-resolution.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Effective model construction for enhanced prediction in example-based super-resolution.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
Efficient Memory-Addressing Algorithms for FFT Processor Design.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Low-Complexity High-Throughput QR Decomposition Design for MIMO Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Depth-Reliability-Based Stereo-Matching Algorithm and Its VLSI Architecture Design.
IEEE Trans. Circuits Syst. Video Technol., 2015

Blind Channel Estimation for CP/CP-Free OFDM Systems Using Subspace Approach.
Proceedings of the IEEE 81st Vehicular Technology Conference, 2015

Efficient highly-parallel turbo decoder for 3GPP LTE-Advanced.
Proceedings of the VLSI Design, Automation and Test, 2015

High-quality texture compression using adaptive color grouping and selection algorithm.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Scalable Montgomery Modular Multiplication Architecture with Low-Latency and Low-Memory Bandwidth Requirement.
IEEE Trans. Computers, 2014

Subspace-Based Blind Channel Estimation for MIMO-OFDM Systems with New Signal Permutation Method.
Proceedings of the IEEE 79th Vehicular Technology Conference, 2014

Low complexity stereo matching algorithm using adaptive sized square window.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Low-complexity architecture for Chase soft-decision Reed-Solomon decoding.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

An efficient countermeasure against power attacks for ECC over GF(p).
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Guest Editorial Special Section on the 2012 IEEE International Symposium on Circuits and Systems (ISCAS 2012).
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Reactivation of Spares for Off-Chip Memory Repair After Die Stacking in a 3-D IC With TSVs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Subspace-Based Blind Channel Estimation by Separating Real and Imaginary Symbols for Cyclic-Prefixed Single-Carrier Systems.
IEEE Trans. Broadcast., 2013

Low-complexity multi-standard variable length coding decoder using tree-based partition and classification.
IET Image Process., 2013

Subspace-Based Blind Channel Estimation for MIMO-OFDM Systems with Repetition Index.
Proceedings of the 78th IEEE Vehicular Technology Conference, 2013

Energy-efficient architecture for word-based Montgomery modular multiplication algorithm.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

2012
Implementations of Signal-Processing Algorithms for OFDM Systems.
J. Electr. Comput. Eng., 2012

Blind channel estimation for cyclic prefix-free orthogonal frequency-division multiplexing systems with particular input symbols.
IET Commun., 2012

Low-Complexity Memory Access Architectures for Quasi-Cyclic LDPC Decoders.
IEICE Trans. Inf. Syst., 2012

Efficient architecture for Reed-Solomon decoder.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Fast scalable radix-4 Montgomery modular multiplier.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Efficient scissoring scheme for scanline-based rendering of 2D vector graphics.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

An efficient QR decomposition design for MIMO systems.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A low-latency turbo decoding scheme for diversities-based communication systems.
Proceedings of the 6th International Conference on Signal Processing and Communication Systems, 2012

High-performance turbo-MIMO system design with iterative soft-detection and decoding.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2012

Face detection architecture design using hybrid skin color detection and cascade of classifiers.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

Blind channel estimation for MIMO-OFDM systems with repeated time-domain symbols.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011
Design of High-Speed Iterative Dividers in GF(2<sup>m</sup>).
J. Inf. Sci. Eng., 2011

Reconfigurable Homogenous Multi-Core FFT Processor Architectures for Hybrid SISO/MIMO OFDM Wireless Communications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Design and Implementation of a Low-Complexity Reed-Solomon Decoder for Optical Communication Systems.
IEICE Trans. Inf. Syst., 2011

VLSI design of area-efficient memory access architectures for quasi-cyclic LDPC codes.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

2010
A High-Performance Unified-Field Reconfigurable Cryptographic Processor.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Reconfigurable architecture for entropy decoding and inverse transform in H.264.
IEEE Trans. Consumer Electron., 2010

Low-cost FFT processor for DVB-T2 applications.
IEEE Trans. Consumer Electron., 2010

Word-Based Montgomery Modular Multiplication Algorithm for Low-Latency Scalable Architectures.
IEEE Trans. Computers, 2010

High-Speed Low-Complexity Architecture for Reed-Solomon Decoders.
IEICE Trans. Inf. Syst., 2010

Blind Channel Estimation for SIMO-OFDM Systems without Cyclic Prefix.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Subspace-Based Blind Channel Estimation for OFDM Systems with Conjugate-Symmetric Property.
Proceedings of the 71st IEEE Vehicular Technology Conference, 2010

Efficient memory management for FFT processors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Low-complexity Reed-Solomon decoder for optical communications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Design of high-speed bit-serial divider in GF(2<sup>m</sup>).
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Area-Efficient H.264 VLC Decoder Using Sub-tree Classification.
Proceedings of the Sixth International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2010), 2010

Efficient protocol converter generation for system integration.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

A signal permutation method for cyclic-prefix-free OFDM channel estimation.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
A New Algorithm for High-Speed Modular Multiplication Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

An Efficient Multiplier/Divider Design for Elliptic Curve Cryptosystem over GF(2m).
J. Inf. Sci. Eng., 2009

Low-power register-exchange survivor memory architectures for Viterbi decoders.
IET Circuits Devices Syst., 2009

Design of a High-Throughput CABAC Encoder.
IEICE Trans. Inf. Syst., 2009

Modified Subspace Based Channel Estimation Algorithm for OFDM Systems.
Proceedings of the 69th IEEE Vehicular Technology Conference, 2009

Flexible GF(2<sup>m</sup>) Divider Design for Cryptographic Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A Generalized Blind Channel Estimation Algorithm for OFDM Systems with Cyclic Prefix.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Efficient Software-Based Self-Test Methods for Embedded Digital Signal Processors.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

Hardware/Software Codesign of Resource Constrained Real-Time Systems.
Proceedings of the Fifth International Conference on Information Assurance and Security, 2009

2008
A New Modular Exponentiation Architecture for Efficient Design of RSA Cryptosystem.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Algorithms of Finding the First Two Minimum Values and Their Hardware Implementation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Reducing Interconnect Complexity for Efficient Path Metric Memory Management in Viterbi Decoders.
IEICE Trans. Inf. Syst., 2008

A new look-up table-based multiplier/squarer design for cryptosystems over GF(2<sup>m</sup>).
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

High-speed modular multiplication design for public-key cryptosystems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Exploration of Low-Cost Configurable S-Box Designs for AES Applications.
Proceedings of the International Conference on Embedded Software and Systems, 2008

Design of square generator with small look-up table.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
A New Montgomery Modular Multiplication Algorithm and its VLSI Design for RSA Cryptosystem.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
High-Speed Design of Montgomery Inverse Algorithm over GF(2<sup><i>m</i></sup>).
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Efficient path metric access for reducing interconnect overhead in Viterbi decoders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Design and implementation of efficient Reed-Solomon decoders for multi-mode applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

High-speed CRC design for 10 Gbps applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Asynchronous Design of Modular Multiplication Using Adaptive Radix Computation.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
VLSI architectural design tradeoffs for sliding-window log-MAP decoders.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Concurrent algorithm for high-speed point multiplication in elliptic curve cryptography.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m).
IEEE Trans. Computers, 2004

VLSI architecture exploration for sliding-window Log-MAP decoders.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Implementation of channel demodulator for DAB system.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
An area-efficient systolic division circuit over GF(2/sup m/) for secure communication.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Memory arrangements in turbo decoders using sliding-window BCJR algorithm.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
A Systematic Approach for Parallel CRC Computations.
J. Inf. Sci. Eng., 2001

Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

VLSI architecture of extended in-place path metric update for Viterbi decoders.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A novel adaptive algorithm and VLSI design for frequency detection in noisy environment based on adaptive IIR filter.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Design of an efficient FFT processor for DAB system.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
An efficient approach for in-place scheduling of path metric update in Viterbi decoders.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

High-speed generation of LFSR signatures.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999
Design and implementation of a DAB channel decoder.
IEEE Trans. Consumer Electron., 1999

A VLSI architecture of fast high-radix modular multiplication for RSA cryptosystem.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

An area-efficient versatile Reed-Solomon decoder for ADSL.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998
Design of a High-Speed Square Generator.
IEEE Trans. Computers, 1998

1996
A CAM-Based VLSI Architecture for Shared Buffer ATM Switch with Fuzzy Controlled Buffer Management.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

1993
ASLCScan: A Scan Design Technique for Asynchronous Sequential Logic Circuits.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993


  Loading...