Tsung-Hsien Tsai
Orcid: 0000-0001-6440-2146
According to our database1,
Tsung-Hsien Tsai
authored at least 24 papers
between 2007 and 2022.
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Bibliography
2022
Discovering a trans-omics biomarker signature that predisposes high risk diabetic patients to diabetic kidney disease.
npj Digit. Medicine, 2022
A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
J. Vis. Commun. Image Represent., 2021
2020
Self-evolutionary sibling models to forecast railway arrivals using reservation data.
Eng. Appl. Artif. Intell., 2020
Embedded PLL Phase Noise Measurement Based on a PFD/CP MASH 1-1-1 ΔΣ Time-to-Digital Converter in 7nm CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
A 4-to-18GHz Active Poly Phase Filter Quadrature Clock Generator with Phase Error Correction in 5nm CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2018
A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
2017
A Cooperative Multihop Transmission Scheme for Two-Way Amplify-and-Forward Relay Networks.
IEEE Trans. Veh. Technol., 2017
Proceedings of the 2017 IEEE International Conference on Image Processing, 2017
2016
Comparison of Several Confidence Intervals for Median Residual Lifetime with Left-truncated and Right-censored Data.
Commun. Stat. Simul. Comput., 2016
A 0.034mm<sup>2</sup>, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Proceedings of the 10th International Symposium on Communication Systems, 2016
2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Real-time vehicle color identification using symmetrical SURFs and chromatic strength.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2013
Proceedings of the IEEE International Conference on Vehicular Electronics and Safety, 2013
Proceedings of the IEEE International Conference on Information and Automation, 2013
A 0.1-3GHz cell-based fractional-N all digital phase-locked loop using ΔΣ noise-shaped phase detector.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2010
Algorithm and Architecture of Disparity Estimation With Mini-Census Adaptive Support Weight.
IEEE Trans. Circuits Syst. Video Technol., 2010
2009
Neural network based temporal feature models for short-term railway passenger demand forecasting.
Expert Syst. Appl., 2009
Expert Syst. Appl., 2009
2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Case Based Models to Predict Final Sales: A Test of Railway Passenger Arrivals.
Proceedings of The 2008 International Conference on Data Mining, 2008
2007
Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, 2007