Chien-Ming Wu

According to our database1, Chien-Ming Wu authored at least 52 papers between 1999 and 2020.

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Bibliography

2020
Intraseasonal Vertical Cloud Regimes Based on CloudSat Observations over the Tropics.
Remote. Sens., 2020

2019
A Cost-Effective Modified Bright-Mode Automatic Prism Coupler for Planar Optical Waveguide Characterization.
IEEE Trans. Educ., 2019

Learning the Representations of Moist Convection with Convolutional Neural Networks.
CoRR, 2019

A Smart Sensor Development Platform and Its System Demonstration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2017
A modular wireless sensor platform and its applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
A rugged sensor system for real-time bridge safety monitoring in Taiwan.
Proceedings of the IEEE Sensors Applications Symposium, 2016

A real-time bridge scour sensor system with accelerometers.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2016

Live demonstration: MorFPGA duo platform with dual-camera support.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
A Cost-Effective 3D SoC Silicon Prototyping Platform.
J. Inf. Sci. Eng., 2015

A real-time bridge structural health monitoring device using cost-effective one-axis accelerometers.
Proceedings of the Tenth IEEE International Conference on Intelligent Sensors, 2015

2014
Structural health monitoring of bridges using cost-effective 1-axis accelerometers.
Proceedings of the IEEE Sensors Applications Symposium, 2014

Live demonstration: A 3D die-level integration platform.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
Morpack Cube: A portable 3D heterogeneous system integration platform.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

2012
An efficient memory controller for 3D heterogeneous integration platform.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

A novel design methodology for hybrid process 3D-IC.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

A novel design flow for a 3D heterogeneous system prototyping platform.
Proceedings of the IEEE 25th International SOC Conference, 2012

Boundary scan test solution for MorPACK platform.
Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2012

CIC signal processing embedded system a modulizable platform for multi-domain signal processing.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012

A modularized 3D heterogeneous system integration platform.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011
Programmable System-on-Chip for Silicon Prototyping.
IEEE Trans. Ind. Electron., 2011

Design of High-Speed Iterative Dividers in GF(2<sup>m</sup>).
J. Inf. Sci. Eng., 2011

A novel methodology for Multi-Project System-on-a-Chip.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Application-oriented teaching of embedded systems.
Proceedings of the 2011 IEEE International Conference on Microelectronic Systems Education, 2011

A complex event processing architecture for energy and operation management: industrial experience report.
Proceedings of the Fifth ACM International Conference on Distributed Event-Based Systems, 2011

2010
Efficient memory management for FFT processors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Low-complexity Reed-Solomon decoder for optical communications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Design of high-speed bit-serial divider in GF(2<sup>m</sup>).
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
An Efficient Multiplier/Divider Design for Elliptic Curve Cryptosystem over GF(2m).
J. Inf. Sci. Eng., 2009

True Event Decision by Cooperative Sensor Network.
Proceedings of the MDM 2009, 2009

Flexible GF(2<sup>m</sup>) Divider Design for Cryptographic Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Implementation and Prototyping of a Complex Multi-project System-on-a-chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
Reducing Interconnect Complexity for Efficient Path Metric Memory Management in Viterbi Decoders.
IEICE Trans. Inf. Syst., 2008

PrSoC: Programmable System-on-chip (SoC) for silicon prototyping.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
Reduction of image coding artifacts using spatial structure analysis.
Proceedings of the 9th International Symposium on Signal Processing and Its Applications, 2007

2006
High-Speed Design of Montgomery Inverse Algorithm over GF(2<sup><i>m</i></sup>).
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Efficient path metric access for reducing interconnect overhead in Viterbi decoders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
VLSI architectural design tradeoffs for sliding-window log-MAP decoders.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Concurrent algorithm for high-speed point multiplication in elliptic curve cryptography.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

High-performance low-complexity bit-plane coding scheme for MPEG-4 FGS.
Proceedings of the 2005 IEEE International Conference on Multimedia and Expo, 2005

2004
High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m).
IEEE Trans. Computers, 2004

VLSI architecture exploration for sliding-window Log-MAP decoders.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A high-performance area-aware DSP processor architecture for video codecs.
Proceedings of the 2004 IEEE International Conference on Multimedia and Expo, 2004

2003
Implementation of channel demodulator for DAB system.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
An area-efficient systolic division circuit over GF(2/sup m/) for secure communication.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Memory arrangements in turbo decoders using sliding-window BCJR algorithm.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

VLSI architecture of extended in-place path metric update for Viterbi decoders.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Design of an efficient FFT processor for DAB system.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
An efficient approach for in-place scheduling of path metric update in Viterbi decoders.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
Design and implementation of a DAB channel decoder.
IEEE Trans. Consumer Electron., 1999

An area-efficient versatile Reed-Solomon decoder for ADSL.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999


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