Jun-Kai Zhao
According to our database1,
Jun-Kai Zhao
authored at least 5 papers
between 2013 and 2016.
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Bibliography
2016
A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
A 28nm 36kb high speed 6T SRAM with source follower PMOS read and bit-line under-drive.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
A low-power charge sharing hierarchical bitline and voltage-latched sense amplifier for SRAM macro in 28 nm CMOS technology.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
2013
A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013