Yi-Wei Chiu
According to our database1,
Yi-Wei Chiu
authored at least 9 papers
between 2008 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
Proceedings of the 14th IEEE Annual Ubiquitous Computing, 2023
2016
A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
A 28nm 36kb high speed 6T SRAM with source follower PMOS read and bit-line under-drive.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
A low-power charge sharing hierarchical bitline and voltage-latched sense amplifier for SRAM macro in 28 nm CMOS technology.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
2013
A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
2012
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
2011
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008