Ching-Te Chuang
According to our database1,
Ching-Te Chuang
authored at least 133 papers
between 1996 and 2019.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 1994, "For contributions to high-performance bipolar devices, circuits, and technology.".
Timeline
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Bibliography
2019
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
2018
28nm near/sub-threshold dual-port FIFO memory for shared queues in multi-sensor applications.
Proceedings of the 2018 International Symposium on VLSI Design, 2018
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018
2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Ultrahigh-Density 256-Channel Neural Sensing Microsystem Using TSV-Embedded Neural Probes.
IEEE Trans. Biomed. Circuits Syst., 2017
An implantable 128-channel wireless neural-sensing microsystem using TSV-embedded dissolvable μ-needle array and flexible interposer.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Exploration and evaluation of low-dropout linear voltage regulator with FinFET, TFET and hybrid TFET-FinFET implementations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
A 0.35 V, 375 kHz, 5.43 µW, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line.
Microelectron. J., 2016
Area-power-efficient 11-bit hybrid dual-Vdd ADC with self-calibration for neural sensing application.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016
Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
An ultra-high-density 256-channel/25mm2 neural sensing microsystem using TSV-embedded neural probes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Investigation of BTI reliability for monolithic 3D 6T SRAM with ultra-thin-body GeOI MOSFETs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Exploration and evaluation of hybrid TFET-MOSFET monolithic 3D SRAMs considering interlayer coupling.
Proceedings of the International Conference on IC Design and Technology, 2016
2015
A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Low power algorithm-architecture co-design of fast Independent Component Analysis (FICA) for multi-gas sensor applications.
Proceedings of the VLSI Design, Automation and Test, 2015
All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction.
Proceedings of the VLSI Design, Automation and Test, 2015
Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Evaluation of TFET and FinFET devices and 32-Bit CLA circuits considering work function variation and line-edge roughness.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Evaluation of 32-Bit carry-look-ahead adder circuit with hybrid tunneling FET and FinFET devices.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
2014
Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors.
IEEE Trans. Circuits Syst. II Express Briefs, 2014
A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
2.5D Heterogeneously Integrated Microsystem for High-Density Neural Sensing Applications.
IEEE Trans. Biomed. Circuits Syst., 2014
Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits.
Microelectron. Reliab., 2014
Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014
Energy-efficient low-noise 16-channel analog-front-end circuit for bio-potential acquisition.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
18.6 2.5D heterogeneously integrated bio-sensing microsystem for multi-channel neural-sensing applications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Energy-efficient configurable discrete wavelet transform for neural sensing applications.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Investigation and optimization of monolithic 3D logic circuits and SRAM cells considering interlayer coupling.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
A disturb-free subthreshold 9T SRAM cell with improved performance and variation tolerance.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013
Method for resolving simultaneous same-row access in Dual-Port 8T SRAM with asynchronous dual-clock operation.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013
A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013
Through-silicon-via-based double-side integrated microsystem for neural sensing applications.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Device design and analysis of logic circuits and SRAMs for Germanium FinFETs on SOI and bulk substrates.
Proceedings of the International Symposium on Quality Electronic Design, 2013
A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Near-/Sub-Vth process, voltage, and temperature (PVT) sensors with dynamic voltage selection.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Impacts of single trap induced random telegraph noise on Si and Ge nanowire FETs, 6T SRAM cells and logic circuits.
Proceedings of 2013 International Conference on IC Design & Technology, 2013
Area-power-efficient 11-bit SAR ADC with delay-line enhanced tuning for neural sensing applications.
Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
A 0.33-V, 500-kHz, 3.94-µW 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
IEEE Trans. Circuits Syst. II Express Briefs, 2012
A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing.
IEEE J. Solid State Circuits, 2012
Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
Proceedings of the IEEE 25th International SOC Conference, 2012
Proceedings of the IEEE 25th International SOC Conference, 2012
Proceedings of the 2012 IEEE International Test Conference, 2012
A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Impacts of random telegraph noise on the analog properties of FinFET and trigate devices and Widlar current source.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012
Stability and performance optimization of InGaAs-OI and GeOI hetero-channel SRAM cells.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012
A comparative analysis of tunneling FET circuit switching characteristics and SRAM stability and performance.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
A comprehensive comparative analysis of FinFET and Trigate device, SRAM and logic circuits.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
2011
Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High-kappa Metal-Gate Devices.
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Impacts of NBTI/PBTI on Timing Control Circuits and Degradation Tolerant Design in Nanoscale CMOS SRAM.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
2009
Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability.
Microelectron. Reliab., 2009
Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics.
IEEE J. Solid State Circuits, 2009
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
A Precise Negative Bias Temperature Instability Sensor using Slew-rate Monitor Circuitry.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
Microelectron. J., 2008
An On-Chip Test Structure and Digital Measurement Method for Statistical Characterization of Local Random Variability in a Process.
IEEE J. Solid State Circuits, 2008
Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield.
Proceedings of the 26th International Conference on Computer Design, 2008
2007
Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices.
Microelectron. J., 2007
A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Statistical Characterization and On-Chip Measurement Methods for Local Random Variability of a Process Using Sense-Amplifier-Based Test Structure.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
2005
Direct Temperature Measurement for VLSI Circuits and 3-D Modeling of Self-Heating in Sub-0.13 mum SOI Technologies.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
2004
Restoration of controllable hysteresis in partially depleted SOI CMOS Schmitt trigger circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2004
A Novel Technique For Steady State Analysis For VLSI Circuits In Partially Depleted SOI.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
Proceedings of the 33rd European Solid-State Circuits Conference, 2004
2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
Microelectron. Reliab., 2003
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
New digital circuit techniques for total standby leakage reduction in nano-scale SOI technology.
Proceedings of the ESSCIRC 2003, 2003
2002
Microelectron. Reliab., 2002
2001
On the temperature dependence of hysteresis effect in floating-body partially depleted SOI CMOS circuits.
IEEE J. Solid State Circuits, 2001
Dynamic body charge modulation for sense amplifiers in partially depleted SOI technology.
IEEE J. Solid State Circuits, 2001
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001
2000
IEEE J. Solid State Circuits, 2000
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000
A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000
"Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session).
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000
1999
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999
Proceedings of the 36th Conference on Design Automation, 1999
1998
1997
IEEE J. Solid State Circuits, 1997
IEEE J. Solid State Circuits, 1997
Circuit design techniques for the high-performance CMOS IBM S/390 Parallel Enterprise Server G4 microprocessor.
IBM J. Res. Dev., 1997
1996
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996