Yuan-Hua Chu

According to our database1, Yuan-Hua Chu authored at least 36 papers between 1995 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
A Sustainable Soil Energy Harvesting System With Wide-Range Power-Tracking Architecture.
IEEE Internet Things J., 2019

2018
MORAS: An energy-scalable system using adaptive voltage scaling.
Proceedings of the 2018 International Symposium on VLSI Design, 2018

A Wide-Range Capacitive DC-DC Converter with 2D-MPPT for Soil/Solar Energy Extraction.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

A 99.2% Tracking Accuracy Single-Inductor Quadruple-Input-Quadruple-Output Buck-Boost Converter Topology with Periodical Interval Perturbation and Observation MPPT.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2016
A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques.
IEICE Trans. Electron., 2016

Invited - Wireless sensor nodes for environmental monitoring in internet of things.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
A Near-Threshold Cell-Based All-Digital PLL with Hierarchical Band-Selection G-DCO for Fast Lock-In and Low-Power Applications.
IEICE Trans. Electron., 2015

All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction.
Proceedings of the VLSI Design, Automation and Test, 2015

An all-digital power management unit with 90% power efficiency and ns-order voltage transition time for DVS operation in low power sensing SoC applications.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
A Wide-Range Level Shifter Using a Modified Wilson Current Mirror Hybrid Buffer.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

A radio-controlled receiver for clocks/watches and alarm applications.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

An ultra-low voltage hearing aid chip using variable-latency design technique.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Low power fixed-latency DSP accelerator with autonomous minimum energy tracking (AMET).
Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014

A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm<sup>2</sup> all-digital delay-locked loop in 65-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
An Adaptive Pulse-Triggered Flip-Flop for a High-Speed and Voltage-Scalable Standard Cell Library.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-V<sub>TH</sub> Read-Port, and Offset Cell VDD Biasing Techniques.
IEEE J. Solid State Circuits, 2013

A dual-edged triggered explicit-pulsed level converting flip-flop with a wide operation range.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques.
Proceedings of the Symposium on VLSI Circuits, 2012

An energy-efficient level converter with high thermal variation immunity for sub-threshold to super-threshold operation.
Proceedings of the IEEE 25th International SOC Conference, 2012

An ultra-low power interface CMOS IC design for biosensor applications.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Thermoelectric energy harvesting with 1mV low input voltage and 390nA quiescent current for 99.6% maximum power point tracking.
Proceedings of the 38th European Solid-State Circuit conference, 2012

Energy-efficient RISC design with on-demand circuit-level timing speculation.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Parallel Architecture Core (PAC) - the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools.
J. Signal Process. Syst., 2011

A Large Sigma V <sub>TH</sub> /VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme.
IEEE J. Solid State Circuits, 2011

0.5 VDD digitally controlled oscillators design with compensation techniques for PVT variations.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
Energy-efficient real-time scheduling of multimedia tasks on multi-core processors.
Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), 2010

A 0.29V embedded NAND-ROM in 90nm CMOS for ultra-low-voltage applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Collaborative voltage scaling with online STA and variable-latency datapath.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009
Full System Simulation and Verification Framework.
Proceedings of the Fifth International Conference on Information Assurance and Security, 2009

2006
Design of STR level converters for SoCs using the multi-island dual-VDD design technique.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
The new approach of programmable pseudo fractional-N clock generator for GHz operation with 50% duty cycle.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

1995
Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995


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