Shyh-Jye Jou
Orcid: 0000-0002-8821-3486
According to our database1,
Shyh-Jye Jou
authored at least 152 papers
between 1994 and 2023.
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Bibliography
2023
A Digital Frequency-Dependent I/Q Imbalance and Group Delay Estimation and Compensation Modules for mmWave Single Carrier Baseband Transceivers.
IEEE J. Emerg. Sel. Topics Circuits Syst., June, 2023
Low Routing Complexity Multiframe Pipelined LDPC Decoder Based on a Novel Pseudo Marginalized Min-Sum Algorithm for High Throughput Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2023
Offline and Time-variant EVD-based Closed-loop Digital Predistortion Design for Sub-THz Power Amplifier Array in Basedband Transmitter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
A 14 μJ/Decision Keyword-Spotting Accelerator With In-SRAMComputing and On-Chip Learning for Customization.
IEEE Trans. Very Large Scale Integr. Syst., 2022
Joint Digital Online Compensation of TX and RX Time-Varying I/Q Mismatch and DC-Offset in mmWave Transceiver System.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
A 14uJ/Decision Keyword Spotting Accelerator with In-SRAM-Computing and On Chip Learning for Customization.
CoRR, 2022
An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications.
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022
Proceedings of the 18th International Conference on Synthesis, 2022
Compressive Sensing Based Hardware Design for Channel Estimation of Wideband Millimeter Wave Hybrid MIMO System.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Low-Complexity Pseudo Direct Learning Digital Pre-Distortion Architecture for Nonlinearity and Memory Effect of Power Amplifier in mmWave Baseband Transmitter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
A Digital Two-Stage Phase Noise Compensation and rCFO/rSCO Tracking Module for mmW Single Carrier Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2021
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2021
Proceedings of the 18th International SoC Design Conference, 2021
A Low-Jitter ADPLL with Adaptive High-Order Loop Filter and Fine Grain Varactor Based DCO.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
A 75-Gb/s/mm<sup>2</sup> and Energy-Efficient LDPC Decoder Based on a Reduced Complexity Second Minimum Approximation Min-Sum Algorithm.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Design of Downlink Synchronization for Millimeter Wave Cellular System Based on Multipath Division Multiple Access.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
Digital Self-Healing using Smart Sensing Technique for IQ Mismatch and LO Leakage against Non-Flat Path Response in mmWave Communication System.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
A 16/64 QAM Baseband SoC for mm-Wave Transceiver with Self-Healing for FD/FI IQ Mismatch, LO Leakage and CFO/SCO/PNC.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020
2019
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019
A 50 Gb/s Adaptive Dual Data-Paths NS-EICL ADFE with 50 Parallelisms for 2-PAM Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Sub-ns Access Sub-mW/GHz 32 Kb SRAM with 0.45 V Cross-Point-5T Cell and Built-in Y_ Line.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
Synthesizable Injection-Locked Phase-Locked Loop with Multiphase Interlocking Digitally Controlled Oscillator Arrays.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
A 40Gb/s All-Digital Adaptive Noise-Suppression Feed-Forward Filter and Adaptive Decision Feedback Equalizer with 40 parallelisms for 2-PAM Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Digital Self-Interference Cancellation for OFDM Full-Duplex Transmission in 60 GHz Band.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Dual-Mode All-Digital Baseband Receiver With a Feed-Forward and Shared-Memory Architecture for Dual-Standard Over 60 GHz NLOS Channel.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
A MMSE Joint Feedback Feed-forward Equalizer for FBMC-OQAM Baseband Receiver in the 60 GHz Band.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2017
Residual sampling clocking offset estimation and compensation for FBMC-OQAM baseband receiver in the 60 GHz band.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
Golay-Correlator Window-Based Noise Cancellation Equalization Technique for 60-GHz Wireless OFDM/SC Receiver.
IEEE Trans. Very Large Scale Integr. Syst., 2016
An 8X-Parallelism Memory Access Reordering Polyphase Network for 60 GHz FBMC-OQAM Baseband Receiver.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
A Systematic ANSI S1.11 Filter Bank Specification Relaxation and Its Efficient Multirate Architecture for Hearing-Aid Systems.
IEEE ACM Trans. Audio Speech Lang. Process., 2016
A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques.
IEICE Trans. Electron., 2016
Dynamic Error-Compensated Fixed-Width Booth Multiplier Based on Conditional-Probability of Input Series.
Circuits Syst. Signal Process., 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Error-resilient sequential cells with successive time borrowing for stochastic computing.
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
A Low-Jitter Cell-Based Digitally Controlled Oscillator With Differential Multiphase Outputs.
IEEE Trans. Very Large Scale Integr. Syst., 2015
A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist.
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
A Near-Threshold Cell-Based All-Digital PLL with Hierarchical Band-Selection G-DCO for Fast Lock-In and Low-Power Applications.
IEICE Trans. Electron., 2015
A 802.15.3c/802.11ad dual mode phase noise cancellation for 60 GHz communication systems.
Proceedings of the VLSI Design, Automation and Test, 2015
A 802.15.3c/802.11ad compliant 24 Gb/s FFT processor for 60 GHz communication systems.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015
A 28nm 36kb high speed 6T SRAM with source follower PMOS read and bit-line under-drive.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Gb/s prototyping of 60GHz indoor wireless SC/OFDM transmitter and receiver on FPGA demo system.
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2015
A 3.52 Gb/s mmWave baseband with delayed decision feedback sequence estimation in 40 nm.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
Full-digital high throughput design of adaptive decision feedback equalizers using coefficient-lookahead.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2014
A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Neuromorphic Pitch Based Noise Reduction for Monosyllable Hearing Aid System Application.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Correction to "Low complexity formant estimation adaptive feedback cancellation for hearing aids using pitch based processing".
IEEE ACM Trans. Audio Speech Lang. Process., 2014
Low Complexity Formant Estimation Adaptive Feedback Cancellation for Hearing Aids Using Pitch Based Processing.
IEEE ACM Trans. Audio Speech Lang. Process., 2014
Analysis and implementation of low-power perceptual multiband noise reduction for the hearing aids application.
IET Circuits Devices Syst., 2014
EURASIP J. Adv. Signal Process., 2014
A low-power charge sharing hierarchical bitline and voltage-latched sense amplifier for SRAM macro in 28 nm CMOS technology.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
An IEEE 802.15.3c/802.11ad compliant SC/OFDM dual-mode baseband receiver for 60 GHz Band.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
An efficient 18-band quasi-ANSI 1/3-octave filter bank using re-sampling method for digital hearing aids.
Proceedings of the IEEE International Conference on Acoustics, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
IEICE Trans. Electron., 2013
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013
A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013
A pitch based VAD adopting quasi-ANSI 1/3 octave filter bank with 11.3 ms latency for monosyllable hearing aids.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013
A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
A SC/HSI dual-mode baseband receiver with frequency-domain equalizer for IEEE 802.15.3c.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
A 0.33-V, 500-kHz, 3.94-µW 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications.
IEEE J. Solid State Circuits, 2012
A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing.
IEEE J. Solid State Circuits, 2012
IET Circuits Devices Syst., 2012
Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
Proceedings of the 2012 IEEE International Test Conference, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE Biomedical Circuits and Systems Conference, 2012
Proceedings of the 2012 IEEE Biomedical Circuits and Systems Conference, 2012
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
2011
Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design.
IEICE Trans. Electron., 2011
A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
0.5 VDD digitally controlled oscillators design with compensation techniques for PVT variations.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2009
IEEE Trans. Consumer Electron., 2009
IEEE Trans. Circuits Syst. II Express Briefs, 2009
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
A 0.92mm<sup>2</sup> 23.4mW fully-compliant CTC decoder for WiMAX 802.16e application.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
IEEE Trans. Consumer Electron., 2008
Introduction to the Special Section on the 2007 Asian Solid-State Circuits Conference (A-SSCC'07).
IEEE J. Solid State Circuits, 2008
IEEE J. Solid State Circuits, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
IET Circuits Devices Syst., 2007
Proceedings of the 2007 IEEE International SOC Conference, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Novel Programmable FIR Filter Based on Higher Radix Recoding for Low-Power and High-Performance Applications.
Proceedings of the IEEE International Conference on Acoustics, 2007
Concurrent Digital Adaptive Decision Feedback Equalizer for 10GBase-LX4 Ethernet System.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
IEICE Trans. Electron., 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A design flow for multiplierless linear-phase FIR filters: from system specification to Verilog code.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
EURASIP J. Adv. Signal Process., 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
2001
ACM Trans. Design Autom. Electr. Syst., 2001
IEEE J. Solid State Circuits, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
2000
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000
1999
J. Electron. Test., 1999
1998
An all digital phase-locked loop with modified binary search of frequency acquisition.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998
1997
A pipelined multiplier-accumulator using a high-speed, low-power static and dynamic full adder design.
IEEE J. Solid State Circuits, 1997
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
1996
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996
Proceedings of the 1996 European Design and Test Conference, 1996
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996
1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Impulse response fault model and fault extraction for functional level analog circuit diagnosis.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995
1994
An I<sub>DDQ</sub> Based Built-in Concurrent Test Technique for Interconnects in a Boundary-Scan Environment.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Mixed-mode simulation and analog multilevel simulation.
The Kluwer international series in engineering and computer science, Kluwer, ISBN: 978-0-7923-9473-0, 1994