K. M. Chen

According to our database, K. M. Chen authored at least 4 papers between 2006 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2022

High speed (1ns) and low voltage (1.5V) demonstration of 8Kb SOT-MRAM array.

M. Y. Song, C. M. Lee, S. Y. Yang, G. L. Chen, K. M. Chen, I J. Wang, Y. C. Hsin, K. T. Chang, C. F. Hsu, S. H. Li, J. H. Wei, T. Y. Lee, M. F. Chang, X. Y. Bao, C. H. Diaz, S. J. Lin

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2008

Reliability evaluation of BOAC and normal pad stacked-chip packaging using low-K wafers.

K. M. Chen, K. H. Tang, J. S. Liu

Microelectron. Reliab., 2008

2006

An investigation into the effects of probing and wire bonding stress on the reliability of BOAC.

K. M. Chen, B. C. Wu, K. H. Tang, F. Y. Cheng, N. H. Kao, J. Y. Lai

Microelectron. Reliab., 2006

Effects of underfill materials on the reliability of low-K flip-chip packaging.

K. M. Chen, D. S. Jiang, N. H. Kao, J. Y. Lai

Microelectron. Reliab., 2006