Kailash Chandra Ray

Somanath Tripathy

IEEE Syst. J., March, 2024

2023

An Efficient Fault-Tolerant Instruction Decoder for RISC-V Based Dual-Core Soft-Processors.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

VLSI Architecture of Modified Complex Harmonic Wavelet Transform.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., December, 2023

VLSI Architecture of DCT-Based Harmonic Wavelet Transform for Time-Frequency Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2023

An energy-efficient single-cycle RV32I microprocessor for edge computing applications.

[BibT_eX]

[DOI]

Satyam Shukla

Punyesh Kumar Jha

Integr., 2023

2022

An Efficient DCT-II Based Harmonic Wavelet Transform for Time-Frequency Analysis.

[BibT_eX]

[DOI]

J. Signal Process. Syst., December, 2022

An Efficient Method for Detection and Localization of Myocardial Infarction.

[BibT_eX]

[DOI]

Garima Sahu

IEEE Trans. Instrum. Meas., 2022

A Low Computational Complexity Modified Complex Harmonic Wavelet Transform.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2022

A Low-Overhead Reconfigurable RISC-V Quad-Core Processor Architecture for Fault-Tolerant Applications.

[BibT_eX]

[DOI]

Satyam Shukla

IEEE Access, 2022

An Efficient Signal Processing Technique for Automated Cardiovascular Disease Detection.

[BibT_eX]

[DOI]

Garima Sahu

Akanksha Gupta

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

2021

ASIC Implementation of Low PAPR Multidevice Variable-Rate Architecture for IEEE 802.11ah.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2021

2020

A Coupled Variable Input LCG Method and its VLSI Architecture for Pseudorandom Bit Generation.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2020

High-Speed Area-Efficient VLSI Architecture of Three-Operand Binary Adder.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

Multiuser Variable Rate GO-OFDMA Architecture and Its FPGA Prototype.

[BibT_eX]

[DOI]

IEEE Syst. J., 2020

2019

Performance Analysis and FPGA Prototype of Variable Rate GO-OFDMA Baseband Transmission Scheme.

[BibT_eX]

[DOI]

Wirel. Pers. Commun., 2019

CORDIC-Based VLSI Architectures of Running DFT with Refreshing Mechanism.

[BibT_eX]

[DOI]

Anindya Sundar Dhar

J. Signal Process. Syst., 2019

Modified Dual-CLCG Method and its VLSI Architecture for Pseudorandom Bit Generation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Blind Detection and Classification Algorithm for Smart Audio Monitoring System.

[BibT_eX]

[DOI]

Vivek Singh

Somanath Tripathy

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

Design and ASIC Implementation of a Reconfigurable Fault-Tolerant ALU for Space Applications.

[BibT_eX]

[DOI]

Satyam Shukla

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

An Efficient Signal Processing Technique for Automated Myocardial Infarction Detection.

[BibT_eX]

[DOI]

Garima Sahu

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

Area-Efficient Parallel-Prefix Binary Comparator.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

A Basis Function for DCT Based Discrete Orthogonal S-Transform.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

2018

An Efficient VLSI Architecture for Computation of Discrete Fractional Fourier Transform.

[BibT_eX]

[DOI]

M. V. N. V. Prasad

Anindya Sundar Dhar

J. Signal Process. Syst., 2018

FPGA Prototype and Real Time Analysis of Multiuser Variable Rate CI-GO-OFDMA.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2018

A Personalized Point-of-Care Platform for Real-Time ECG Monitoring.

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., 2018

Sparse representation of ECG signals for automated recognition of cardiac arrhythmias.

[BibT_eX]

[DOI]

Expert Syst. Appl., 2018

Automated recognition of cardiac arrhythmias using sparse decomposition over composite dictionary.

[BibT_eX]

[DOI]

Comput. Methods Programs Biomed., 2018

2017

ECG Signal Analysis Using DCT-Based DOST and PSO Optimized SVM.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2017

A VLSI architecture of CORDIC-based popular windows and its FPGA prototype.

[BibT_eX]

[DOI]

Vikas Kumar

Preetam Kumar

Int. J. High Perform. Syst. Archit., 2017

Application of variational mode decomposition and ABC optimized DAG-SVM in arrhythmia analysis.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017

Single cycle RISC-V micro architecture processor and its FPGA prototype.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017

2016

Dynamic Hash key-based stream cipher for secure transmission of real time ECG signal.

[BibT_eX]

[DOI]

Secur. Commun. Networks, 2016

Efficient methodology for electrocardiogram beat classification.

[BibT_eX]

[DOI]

Piyush Sharma

IET Signal Process., 2016

Cardiac arrhythmia beat classification using DOST and PSO tuned SVM.

[BibT_eX]

[DOI]

Om Shankar

Comput. Methods Programs Biomed., 2016

2015

Non-singular sequence folding-based pseudorandom key generation algorithm for cryptographic processor.

[BibT_eX]

[DOI]

Secur. Commun. Networks, 2015

ARM-based arrhythmia beat monitoring system.

[BibT_eX]

[DOI]

G. S. S. Praveen Chand

Microprocess. Microsystems, 2015

Five decade evolution of feedback shift register: algorithms, architectures and applications.

[BibT_eX]

[DOI]

Int. J. Commun. Networks Distributed Syst., 2015

Design and Implementation of Quadruple Floating-Point CORDIC.

[BibT_eX]

[DOI]

Arun Kumar Singh

Madhav Kumar Singh

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

FPGA Prototype of Low Latency BBS PRNG.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

2014

CORDIC-Based VLSI Architecture for Implementing Kaiser-Bessel Window in Real Time Spectral Analysis.

[BibT_eX]

[DOI]

Anindya Sundar Dhar

J. Signal Process. Syst., 2014

Low Latency Hybrid CORDIC Algorithm.

[BibT_eX]

[DOI]

Rohit Shukla

IEEE Trans. Computers, 2014

CORDIC-based VLSI architecture for real time implementation of flat top window.

[BibT_eX]

[DOI]

Vikas Kumar

Preetam Kumar

Microprocess. Microsystems, 2014

FPGA implementation of stream cipher using Toeplitz Hash function.

[BibT_eX]

[DOI]

Saptadeep Pal

Proceedings of the 2014 International Conference on Advances in Computing, 2014

2011

Hardware efficient design of Variable Length FFT Processor.

[BibT_eX]

[DOI]

Vinay Gautam

Pauline C. Haddow

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

2008

High Throughput VLSI Architecture for Blackman Windowing in Real Time Spectral Analysis.

[BibT_eX]

[DOI]