Kalyana C. Bollapalli

According to our database1, Kalyana C. Bollapalli authored at least 9 papers between 2009 and 2013.

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Bibliography

2013
A low-jitter phase-locked resonant clock generation and distribution scheme.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

2011
An Automated Approach for Minimum Jitter Buffered H-Tree Construction.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

2010
Implementing digital logic with sinusoidal supplies.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Selective Forward Body Bias for High Speed and Low Power SRAMs.
J. Low Power Electron., 2009

A robust pulsed flip-flop and its use in enhanced scan design.
Proceedings of the 27th International Conference on Computer Design, 2009

A PLL design based on a standing wave resonant oscillator.
Proceedings of the 27th International Conference on Computer Design, 2009

On-chip bidirectional wiring for heavily pipelined systems using network coding.
Proceedings of the 27th International Conference on Computer Design, 2009

Low power and high performance sram design using bank-based selective forward body bias.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Highly parallel decoding of space-time codes on graphics processing units.
Proceedings of the 47th Annual Allerton Conference on Communication, 2009


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