Rajesh Garg

According to our database, Rajesh Garg authored at least 29 papers between 2006 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2012

Patch management automation for enterprise cloud.

Hai Huang, Salman Baset, Chunqiang Tang, Ashu Gupta, K. N. Madhu Sudhan, Fazal Feroze, Rajesh Garg, Sumithra Ravichandran

Proceedings of the 2012 IEEE Network Operations and Management Symposium, 2012

2009

Circuit-Level Design Approaches for Radiation-Hard Digital Electronics.

Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan S. Choi

IEEE Trans. Very Large Scale Integr. Syst., 2009

Encoding Serial Graphical Data for Energy-Delay Product/Energy Minimization.

Sasidharan Ekambavanan, Rajesh Garg, Sunil P. Khatri, Krishna R. Narayanan

J. Low Power Electron., 2009

Selective Forward Body Bias for High Speed and Low Power SRAMs.

Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri

J. Low Power Electron., 2009

Design and implementation of a sub-threshold BFSK transmitter.

Suganth Paul, Rajesh Garg, Sunil P. Khatri, Sheila Vaidya

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

SEU hardened clock regeneration circuits.

Rajballav Dash, Rajesh Garg, Sunil P. Khatri, Gwan S. Choi

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

A radiation tolerant Phase Locked Loop design for digital electronics.

Rajesh Kumar, Vinay Karkala, Rajesh Garg, Tanuj Jindal, Sunil P. Khatri

Proceedings of the 27th International Conference on Computer Design, 2009

A robust pulsed flip-flop and its use in enhanced scan design.

Rajesh Kumar, Kalyana C. Bollapalli, Rajesh Garg, Tarun Soni, Sunil P. Khatri

Proceedings of the 27th International Conference on Computer Design, 2009

A PLL design based on a standing wave resonant oscillator.

Vinay Karkala, Kalyana C. Bollapalli, Rajesh Garg, Sunil P. Khatri

Proceedings of the 27th International Conference on Computer Design, 2009

3D simulation and analysis of the radiation tolerance of voltage scaled digital circuit.

Rajesh Garg, Sunil P. Khatri

Proceedings of the 27th International Conference on Computer Design, 2009

On-chip bidirectional wiring for heavily pipelined systems using network coding.

Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri

Proceedings of the 27th International Conference on Computer Design, 2009

Low power and high performance sram design using bank-based selective forward body bias.

Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Efficient analytical determination of the SEU-induced pulse shape.

Rajesh Garg, Sunil P. Khatri

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Modeling dynamic stability of SRAMS in the presence of single event upsets (SEUs).

Rajesh Garg, Peng Li, Sunil P. Khatri

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A novel, highly SEU tolerant digital circuit design approach.

Rajesh Garg, Sunil P. Khatri

Proceedings of the 26th International Conference on Computer Design, 2008

A robust, fast pulsed flip-flop design.

Arunprasad Venkatraman, Rajesh Garg, Sunil P. Khatri

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Pipelined network of PLA based circuit design.

Suganth Paul, Rajesh Garg, Sunil P. Khatri

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

A lithography-friendly structured ASIC design approach.

Salman Gopalani, Rajesh Garg, Sunil P. Khatri, Mosong Cheng

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements.

Charu Nagpal, Rajesh Garg, Sunil P. Khatri

Proceedings of the Design, Automation and Test in Europe, 2008

A Single-supply True Voltage Level Shifter.

Rajesh Garg, Gagandeep Mallarapu, Sunil P. Khatri

Proceedings of the Design, Automation and Test in Europe, 2008

A fast, analytical estimator for the SEU-induced pulse width in combinational designs.

Rajesh Garg, Charu Nagpal, Sunil P. Khatri

Proceedings of the 45th Design Automation Conference, 2008

2007

Low Power UWB Transceiver Design Using Dynamic Voltage Scaling.

Rajesh Garg, Chunjie Duan, Jinyun Zhang, Sinan Gezici

Proceedings of the IEEE Wireless Communications and Networking Conference, 2007

A methodology for interconnect dimension determination.

Jeff L. Cobb, Rajesh Garg, Sunil P. Khatri

Proceedings of the 2007 International Symposium on Physical Design, 2007

2006

Generalized buffering of PTL logic stages using Boolean division.

Rajesh Garg, Sunil P. Khatri

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

CMOS Comparators for High-Speed and Low-Power Applications.

Eric Menendez, Dumezie Maduike, Rajesh Garg, Sunil P. Khatri

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

On the Improvement of Statistical Static Timing Analysis.

Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

A design flow to optimize circuit delay by using standard cells and PLAs.

Rajesh Garg, Mario Sánchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

A PLA based asynchronous micropipelining approach for subthreshold circuit design.

Nikhil Jayakumar, Rajesh Garg, Bruce Gamache, Sunil P. Khatri

Proceedings of the 43rd Design Automation Conference, 2006

A design approach for radiation-hard digital electronics.

Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan Choi

Proceedings of the 43rd Design Automation Conference, 2006