Nikhil Jayakumar

According to our database1, Nikhil Jayakumar authored at least 31 papers between 2003 and 2013.

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Bibliography

2013
ISPD 2013 expert designer/user session (eds).
Proceedings of the International Symposium on Physical Design, 2013

A low-jitter phase-locked resonant clock generation and distribution scheme.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

2011
An Automated Approach for Minimum Jitter Buffered H-Tree Construction.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

2010
A Simultaneous Input Vector Control and Circuit Modification Technique to Reduce Leakage with Zero Delay Penalty.
ACM Trans. Design Autom. Electr. Syst., 2010

2009
A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Circuit-Level Design Approaches for Radiation-Hard Digital Electronics.
IEEE Trans. Very Large Scale Integr. Syst., 2009

2008
Dynamically De-Skewable Clock Distribution Methodology.
IEEE Trans. Very Large Scale Integr. Syst., 2008

A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations.
Integr., 2008

2007
High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems.
J. VLSI Signal Process., 2007

A Predictably Low-Leakage ASIC Design Style.
IEEE Trans. Very Large Scale Integr. Syst., 2007

A Structured ASIC Design Approach Using Pass Transistor Logic.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

An algorithm to minimize leakage through simultaneous input vector control and circuit modification.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
A probabilistic method to determine the minimum leakage vector for combinational designs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

On the Improvement of Statistical Static Timing Analysis.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Network coding for routability improvement in VLSI.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

A High-Speed Fully-Programmable VLSI Decoder for Regular LDPC Codes.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

A design flow to optimize circuit delay by using standard cells and PLAs.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

A PLA based asynchronous micropipelining approach for subthreshold circuit design.
Proceedings of the 43rd Design Automation Conference, 2006

A design approach for radiation-hard digital electronics.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Non-Manhattan Routing Using a Manhattan Router.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Minimum Energy Near-threshold Network of PLA based Design.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

X-Routing using Two Manhattan Route Instances.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Practical techniques to reduce skew and its variations in buffered clock networks.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

A variation tolerant subthreshold design approach.
Proceedings of the 42nd Design Automation Conference, 2005

A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents.
Proceedings of the 42nd Design Automation Conference, 2005

2004
A novel clock distribution and dynamic de-skewing methodology.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

A metal and via maskset programmable VLSI design methodology using PLAs.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

High-throughput VLSI implementations of iterative decoders and related code construction problems.
Proceedings of the Global Telecommunications Conference, 2004. GLOBECOM '04, Dallas, Texas, USA, 29 November, 2004

2003
An ASIC design methodology with predictably low leakage, using leakage-immune standard cells.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Dos and don'ts of CTL state coverage estimation.
Proceedings of the 40th Design Automation Conference, 2003


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