Kanakagiri Raghavendra

According to our database, Kanakagiri Raghavendra authored at least 7 papers between 2008 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

Router Buffer Caching for Managing Shared Cache Blocks in Tiled Multi-Core Processors.

Joe Augustine, Kanakagiri Raghavendra, John Jose, Madhu Mutyam

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2017

MBZip: Multiblock Data Compression.

Kanakagiri Raghavendra, Biswabandan Panda, Madhu Mutyam

ACM Trans. Archit. Code Optim., 2017

2016

PBC: Prefetched Blocks Compaction.

Kanakagiri Raghavendra, Biswabandan Panda, Madhu Mutyam

IEEE Trans. Computers, 2016

2015

SkipCache: application aware cache management for chip multi-processors.

Tripti S. Warrier, Kanakagiri Raghavendra, Madhu Mutyam

IET Comput. Digit. Tech., 2015

2014

SAMO: store aware memory optimizations.

Kanakagiri Raghavendra, Tripti S. Warrier, Madhu Mutyam

Proceedings of the Computing Frontiers Conference, CF'14, 2014

2012

SkipCache: miss-rate aware cache management.

Kanakagiri Raghavendra, Tripti S. Warrier, Madhu Mutyam

Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2008

Process Variation Aware Issue Queue Design.

Kanakagiri Raghavendra, Madhu Mutyam

Proceedings of the Design, Automation and Test in Europe, 2008