Madhu Mutyam

According to our database1, Madhu Mutyam
  • authored at least 60 papers between 2000 and 2017.
  • has a "Dijkstra number"2 of four.

Timeline

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Bibliography

2017
An Experimental Study on Dynamic Bank Partitioning of DRAM in Chip Multiprocessors.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Concurrent Treaps.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2017

2016
PBC: Prefetched Blocks Compaction.
IEEE Trans. Computers, 2016

CASCADE: Congestion Aware Switchable Cycle Adaptive Deflection Router.
Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016

2015
SkipCache: application aware cache management for chip multi-processors.
IET Computers & Digital Techniques, 2015

2014
Implementation and Analysis of History-Based Output Channel Selection Strategies for Adaptive Routers in Mesh NoCs.
ACM Trans. Design Autom. Electr. Syst., 2014

EFGR: An Enhanced Fine Granularity Refresh Feature for High-Performance DDR4 DRAM Devices.
TACO, 2014

Using packet information for efficient communication in NoCs.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

SFFMap: Set-First Fill mapping for an energy efficient pipelined data cache.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Minimally buffered single-cycle deflection router.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

SAMO: store aware memory optimizations.
Proceedings of the Computing Frontiers Conference, CF'14, 2014

Scattered refresh: An alternative refresh mechanism to reduce refresh cycle time.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Data remapping for an energy efficient burst chop in DRAM memory systems.
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014

2013
Prevention slot flow-control mechanism for low latency torus network-on-chip.
IET Computers & Digital Techniques, 2013

SLIDER: Smart Late Injection DEflection Router for mesh NoCs.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

DeBAR: deflection based adaptive router with minimal buffering.
Proceedings of the Design, Automation and Test in Europe, 2013

An Application-Aware Cache Replacement Policy for Last-Level Caches.
Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013

2012
Fibonacci Codes for Crosstalk Avoidance.
IEEE Trans. VLSI Syst., 2012

Way Sharing Set Associative Cache Architecture.
Proceedings of the 25th International Conference on VLSI Design, 2012

TRACKER: A low overhead adaptive NoC router with load balancing selection strategy.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

SkipCache: miss-rate aware cache management.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011
Timing variation-aware scheduling and resource binding in high-level synthesis.
ACM Trans. Design Autom. Electr. Syst., 2011

Prevention flow-control for low latency torus networks-on-chip.
Proceedings of the NOCS 2011, 2011

BOFAR: buffer occupancy factor based adaptive router for mesh NoCs.
Proceedings of the 4th International Workshop on Network on Chip Architectures, 2011

2009
Selective shielding technique to eliminate crosstalk transitions.
ACM Trans. Design Autom. Electr. Syst., 2009

Process-Variation-Aware Adaptive Cache Architecture and Management.
IEEE Trans. Computers, 2009

Delay-efficient bus encoding techniques.
Microprocessors and Microsystems - Embedded Hardware Design, 2009

2008
Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Word-interleaved cache: an energy efficient data cache architecture.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Power management of variation aware chip multiprocessors.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Process Variation Aware Issue Queue Design.
Proceedings of the Design, Automation and Test in Europe, 2008

Block remap with turnoff: A variation-tolerant cache design technique.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Exploiting on-chip data behavior for delay minimization.
Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

Investigating Simple Low Latency Reliable Multiported Register Files.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Variation Analysis of CAM Cells.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Selective shielding: a crosstalk-free bus encoding technique.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Working with process variation aware caches.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses.
J. Low Power Electronics, 2006

Compiler-directed thermal management for VLIW functional units.
Proceedings of the 2006 ACM SIGPLAN/SIGBED Conference on Languages, 2006

Delay and Energy Efficient Data Transmission for On-Chip Buses.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Delay and peak power minimization for on-chip buses using temporal redundancy.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

2005
Rewriting P systems: improved hierarchies.
Theor. Comput. Sci., 2005

On Characterizing Recursively Enumerable Languages by Insertion Grammars.
Fundam. Inform., 2005

2004
Rewriting Tissue P Systems.
J. UCS, 2004

Length Synchronization Context-Free Grammars.
Journal of Automata, Languages and Combinatorics, 2004

Descriptional Complexity of Rewriting P Systems.
Journal of Automata, Languages and Combinatorics, 2004

A Bus Encoding Technique for Power and Cross-talk Minimization.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Preventing Crosstalk Delay using Fibonacci Representation.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

2003
Array-rewriting P systems.
Natural Computing, 2003

Some Variants in Communication of Parallel Communicating Pushdown Automata.
Journal of Automata, Languages and Combinatorics, 2003

Probabilistic Rewriting P Systems.
Int. J. Found. Comput. Sci., 2003

On a class of P automata.
Int. J. Comput. Math., 2003

2002
A Note on Hybrid P Systems.
Grammars, 2002

Contextual P Systems.
Fundam. Inform., 2002

Improved Results about Universality of P systems.
Bulletin of the EATCS, 2002

Generalized normal form for rewriting P systems.
Acta Inf., 2002

A Survey of Some Variants of P Systems.
Proceedings of the Membrane Computing, International Workshop, 2002

Complexity Issues in Rewriting P Systems.
Proceedings of the Fourth International Workshop on Descriptional Complexity of Formal Systems - DCFS 2002, London, Canada, August 21, 2002

2001
P Systems with Membrane Creation: Universality and Efficiency.
Proceedings of the Machines, 2001

2000
Universality Results for Some Variants of P Systems.
Proceedings of the Multiset Processing, 2000


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