Tripti S. Warrier

According to our database, Tripti S. Warrier authored at least 10 papers between 2012 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

P-Box: A RISC-V Packed-SIMD Approach of Accelerating Edge Workloads on Scalar Embedded Cores.

Simi Sukumaran, Babu P. S., Neel Gala, Tripti S. Warrier

IEEE Access, 2026

2024

Accelerating Cryptographic Algorithms on RISC-V cores using Carryless Multiplication.

Simi Sukumaran, Tripti S. Warrier, Babu P. S., Neel Gala

WiPiEC Journal, 2024

2023

True Random Number Generator based on Voltage-Gated Spintronic structure.

Alisha P. B, Tripti S. Warrier

Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

2021

Evaluation of Bit Manipulation Instructions in Optimization of Size and Speed in RISC-V.

P. S. Babu, Snehashri Sivaraman, Deepa N. Sarma, Tripti S. Warrier

Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

2019

2L-2D Routing for Buffered Mesh Network-on-Chip.

Rose George Kunthara, K. Neethu, Rekha K. James, Simi Zerine Sleeba, Tripti S. Warrier, John Jose

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

2015

SkipCache: application aware cache management for chip multi-processors.

Tripti S. Warrier, Kanakagiri Raghavendra, Madhu Mutyam

IET Comput. Digit. Tech., 2015

2014

SAMO: store aware memory optimizations.

Kanakagiri Raghavendra, Tripti S. Warrier, Madhu Mutyam

Proceedings of the Computing Frontiers Conference, CF'14, 2014

2013

An Application-Aware Cache Replacement Policy for Last-Level Caches.

Tripti S. Warrier, B. Anupama, Madhu Mutyam

Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013

2012

Way Sharing Set Associative Cache Architecture.

C. J. Janraj, T. Venkata Kalyan, Tripti S. Warrier, Madhu Mutyam

Proceedings of the 25th International Conference on VLSI Design, 2012

SkipCache: miss-rate aware cache management.

Kanakagiri Raghavendra, Tripti S. Warrier, Madhu Mutyam

Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012