Qian Zhao

According to our database, Qian Zhao authored at least 38 papers between 2010 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

An eFPGA Generation Suite with Customizable Architecture and IDE.

Morihiro Kuga, Qian Zhao, Yuya Nakazato, Motoki Amagasaki, Masahiro Iida

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., March, 2023

2022

Reconfigurable Neural Network Accelerator and Simulator for Model Implementation.

Yasuhiro Nakahara, Masato Kiyama, Motoki Amagasaki, Qian Zhao, Masahiro Iida

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022

A Study of Reconfigurable Switch Architecture for Chiplets Interconnection.

Hui Meng, Qian Zhao, Takaichi Yoshida

Proceedings of the 2022 Tenth International Symposium on Computing and Networking, CANDAR 2022, 2022

2021

Automation of Domain-specific FPGA-IP Generation and Test.

Yuya Nakazato, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga

Proceedings of the HEART '21: 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2021

Attention Mechanism Driven YOLOv3 on FPGA Acceleration for Efficient Vision Based Defect Inspection.

Longzhen Yu, Qian Zhao, Zhixian Wang

Proceedings of the CSAE 2021: The 5th International Conference on Computer Science and Application Engineering, Sanya, China, October 19, 2021

2020

A Microcode-based Control Unit for Deep Learning Processors.

Qian Zhao, Yasuhiro Nakahara, Motoki Amagasaki, Masahiro Iida, Takaichi Yoshida

Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020

Architecture-aware Cost Function for 3D FPGA Placement Using Convolutional Neural Network.

Qian Zhao, Motoki Amagasaki, Masahiro Iida, Takaichi Yoshida

Proceedings of the Eighth International Symposium on Computing and Networking, 2020

2019

A SLM-based overlay architecture for fine-grained virtual FPGA.

Theingi Myint, Motoki Amagasaki, Qian Zhao, Masahiro Iida

IEICE Electron. Express, 2019

A Novel SLM-Based Virtual FPGA Overlay Architecture.

Theingi Myint, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Masato Kiyama

Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

A Pre-Routing Net Wirelength Prediction Method Using an Optimized Convolutional Neural Network.

Ryota Watanabe, Yuki Katsuda, Qian Zhao, Takaichi Yoshida

Proceedings of the Seventh International Symposium on Computing and Networking Workshops, 2019

Implementation of FPGA Building Platform as a Cloud Service.

Ryota Watanabe, Saika Ura, Qian Zhao, Takaichi Yoshida

Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2019

A Platform-as-a-Service System for FPGA Education and Development.

Qian Zhao, Takaichi Yoshida

Proceedings of the ACM Conference on Global Computing Education, 2019

A Resource Reduced Application-Specific FPGA Switch.

Qian Zhao, Yoshimasa Ohnishi, Masahiro Iida, Takaichi Yoshida

Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019

2018

Enabling FPGA-as-a-Service in the Cloud with hCODE Platform.

Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

IEICE Trans. Inf. Syst., 2018

Three Dimensional FPGA Architecture with Fewer TSVs.

Motoki Amagasaki, Masato Ikebe, Qian Zhao, Masahiro Iida, Toshinori Sueyoshi

IEICE Trans. Inf. Syst., 2018

An Adaptable Scheduling for Self-Reconfigurable Objects.

Mahdillah Mahdillah, Shinya Nakayama, Qian Zhao, Takaichi Yoshida

Proceedings of the Sixth International Symposium on Computing and Networking, 2018

2017

Towards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost.

Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

IPSJ Trans. Syst. LSI Des. Methodol., 2017

hCODE 2.0: An open-source toolkit for building efficient FPGA-enabled clouds.

Qian Zhao, Hendarmawan, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the International Conference on Field Programmable Technology, 2017

A Study of FPGA Virtualization and Accelerator Scheduling.

Qian Zhao, Masahiro Iida, Toshinori Sueyoshi

Proceedings of the first Workshop on Emerging Technologies for software-defined and reconfigurable hardware-accelerated Cloud Datacenters, 2017

2016

A Study of Heterogeneous Computing Design Method based on Virtualization Technology.

Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

SIGARCH Comput. Archit. News, 2016

hCODE: An open-source platform for FPGA accelerators.

Qian Zhao, Takuya Nakamichi, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

2015

A 3D FPGA Architecture to Realize Simple Die Stacking.

Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

IPSJ Trans. Syst. LSI Des. Methodol., 2015

Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC.

Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

IEICE Trans. Inf. Syst., 2015

Architecture exploration of 3D FPGA to minimize internal layer connection.

Motoki Amagasaki, Yuto Takeuchi, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Simple wafer stacking 3D-FPGA architecture.

Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 2015 International Conference on IC Design & Technology, 2015

2014

A novel three-dimensional FPGA architecture with high-speed serial communication links.

Takuya Kajiwara, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morituro Kuga, Toshinori Sueyoshi

Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory.

Qian Zhao, Kyosei Yanagida, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2013

FPGA Design Framework Combined with Commercial VLSI CAD.

Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

IEICE Trans. Inf. Syst., 2013

Three-dimensional stacking FPGA architecture using face-to-face integration.

Tetsuro Hamada, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

An FPGA design and implementation framework combined with commercial VLSI CADs.

Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

An automatic FPGA design and implementation framework.

Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Defect-robust FPGA architectures for intellectual property cores in system LSI.

Motoki Amagasaki, Kazuki Inoue, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A novel FPGA design framework with VLSI post-routing performance analysis (abstract only).

Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

2012

COGRE: A Novel Compact Logic Cell Architecture for Area Minimization.

Masahiro Iida, Motoki Amagasaki, Yasuhiro Okamoto, Qian Zhao, Toshinori Sueyoshi

IEICE Trans. Inf. Syst., 2012

2011

A Novel Soft Error Detection and Correction Circuit for Embedded Reconfigurable Systems.

Qian Zhao, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi

IEEE Embed. Syst. Lett., 2011

A novel reconfigurable logic device base on 3D stack technology.

Qian Zhao, Yusuke Iwai, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi

Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010

A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core.

Kazuki Inoue, Qian Zhao, Yasuhiro Okamoto, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi

ACM Trans. Reconfigurable Technol. Syst., 2010

A robust reconfigurable logic device based on less configuration memory logic cell.

Qian Zhao, Yoshihiro Ichinomiya, Yasuhiro Okamoto, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi

Proceedings of the International Conference on Field-Programmable Technology, 2010