Kazuyoshi Nishimura

According to our database, Kazuyoshi Nishimura authored at least 9 papers between 2006 and 2009.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2009

Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit.

Jun Terada, Yusuke Ohtomo, Kazuyoshi Nishimura, Hiroaki Katsurai, Shunji Kimura, Naoto Yoshimoto

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008

A 10.3 Gb/s Burst-Mode CDR Using a ΔΣ DAC.

Jun Terada, Kazuyoshi Nishimura, Shunji Kimura, Hiroaki Katsurai, Naoto Yoshimoto, Yusuke Ohtomo

IEEE J. Solid State Circuits, 2008

A 10-Gb/s Burst-Mode Clock-and-Data Recovery IC with Frequency-Adjusting Dual Gated VCOs.

Yusuke Ohtomo, Masafumi Nogawa, Kazuyoshi Nishimura, Shunji Kimura, Tomoaki Yoshida, Tomoaki Kawamura, Minoru Togashi, Kiyomi Kumozaki

IEICE Trans. Electron., 2008

A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-µm CMOS/SOI.

Yusuke Ohtomo, Hiroshi Koizumi, Kazuyoshi Nishimura, Masafumi Nogawa

IEICE Trans. Electron., 2008

A 10.3125Gb/s Burst-Mode CDR Circuit using a δσ DAC.

Jun Terada, Kazuyoshi Nishimura, Shunji Kimura, Hiroaki Katsurai, Naoto Yoshimoto, Yusuke Ohtomo

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 1ps-Resolution 2ns-Span 10Gb/s Data-Timing Generator with Spectrum Conversion.

Tomoaki Kawamura, Yusuke Ohtomo, Kazuyoshi Nishimura, Noboru Ishihara

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007

High sensitivity APD burst-mode receiver for 10Gbit/s TDM-PON system.

Takashi Nakanishi, Ken-Ichi Suzuki, Youichi Fukada, Naoto Yoshimoto, Makoto Nakamura, Kazutoshi Kato, Kazuyoshi Nishimura, Yusuke Ohtomo, Makoto Tsubokawa

IEICE Electron. Express, 2007

2006

A 12.5-Gb/s Parallel Phase Detection Clock and Data Recovery Circuit in 0.13-$muhbox m$CMOS.

Yusuke Ohtomo, Kazuyoshi Nishimura, Masafumi Nogawa

IEEE J. Solid State Circuits, 2006

A 10Gb/s burst-mode adaptive gain select limiting amplifier in 0.13µm CMOS.

Masafumi Nogawa, Yusuke Ohtomo, Shunji Kimura, Kazuyoshi Nishimura, Tomoaki Kawamura, Minoru Togashi

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006