Hiroaki Katsurai

According to our database1, Hiroaki Katsurai authored at least 13 papers between 2008 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2022
High-power SOA integrated EADFB laser and high-sensitivity burst-mode APD receiver toward 10G- and 25G-class long reach PON.
Proceedings of the 2022 27th OptoElectronics and Communications Conference (OECC) and 2022 International Conference on Photonics in Switching and Computing (PSC), 2022

2021
Practically implementable high-sensitivity 10-Gbit/s avalanche photodiode using inverted p-down design.
IEICE Electron. Express, 2021

2020
A 25G Burst-mode Receiver with -27.7-dBm Sensitivity and 150-ns Response-Time for 50G-EPON Systems.
Proceedings of the European Conference on Optical Communications, 2020

2018
A 25-Gb/s 13 mW clock and data recovery using C<sup>2</sup>MOS D-flip-flop in 65-nm CMOS.
Proceedings of the 2018 International Symposium on VLSI Design, 2018

A 137-mW, 4 ch × 25-Gbps Low-Power Compact Transmitter Flip-Chip-Bonded 1.3-μm LD-Array-on-Si.
Proceedings of the Optical Fiber Communications Conference and Exposition, 2018

2015
A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

2014
20.1-mW 8-Gbps UWB-IR millimeter-wave transmitter using an OOK pulse modulator based on CMOS inverters.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2011
An Injection-Controlled 10-Gb/s Burst-Mode CDR Circuit for a 1G/10G PON System.
IEICE Trans. Electron., 2011

2010
DC-Operated Electrostatic Impact Drive Actuator.
Adv. Robotics, 2010

2009
Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
A 10.3 Gb/s Burst-Mode CDR Using a ΔΣ DAC.
IEEE J. Solid State Circuits, 2008

A 10.3125Gb/s Burst-Mode CDR Circuit using a δσ DAC.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008


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